L1 caches [was boring scheduling stuff]

Larry McVoy (lm@bitmover.com)
Fri, 25 Sep 1998 12:09:43 -0600

: [ Still beats me why L1 data caches don't XOR the low address bits with
: a hash of the high address bits to get the line address, it would fix
: many of the annoying line conflict problems. ]

I'm not sure that there is enough time to do this. Apparently, the path
to the L1 cache is pretty tight. I once did a bunch of work to show
that a large percent of all loads are L1 hits. I don't remember all the
details but the bottom line was that if you could make a processor that
did the load from L1 cache in 1 cycle, i.e., the register is ready for
use at the end of the load instruction cycle, then that would be a 12.5%
performance win across the board.

I shopped the idea around to the MIPS folks and they swore up and down that
there was no way you could do it without increasing the clock.

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