> this timekeeping architecture is already in place. The concept is: all
> processors have a 'local' interrupt, which is used for profiling, process
> time accounting and process timeslice rescheduling. And there is a global
> external interrupt that expires timers.
Yes, I have seen this. On the x86, one processor gets the timer tick
and does the tick processing for the system. Then it signals all the
other processors (via an inter-processor interrupt) to do per-processor
scheduling, and falls through itself. (An alternative would be to send an
interrupt to every processor including itself. That might be simpler
on some systems.)
> you can safely assume that there is globally valid TSC on SMP systems.
> (last i checked this was true for all SMP Intel, Alpha and Sparc systems)
> If you use cli/sti you can make any readout of the TSC value and the timer
> tick counter atomic.
Ah, thank you. I'll go ahead with that assumption, comment it clearly,
and get on with it.
I'd still be interested in figuring out ways to solve the pleisochronous
SMP case though, if anyobdy wants to think about it...
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