David Miller wrote:
> Yes do have to clear them, for two reasons:
>
> 1) So that the hardware MMU doesn't see valid entries after the
> tlb flush. (or in the case of clever software TLB miss strategies
> like that implemeted in the Alpha PAL code or in our sparc64 port,
> making sure the virtual page table mappings go away properly too)
In the hardware case, this isn't true (correct me) if you flush the TLB
after clearing the page directory entries, surely?
We do, and do it right on x86 etc. but that scheme really doesn't
work for the clever Alpha/sparc64 methods in all cases. I discussed
with Linus adding a "flush_tlb_pgtables(mm, begin, end)" method or
similar to deal with this.
I think Alpha might get lucky in this case because it does a full mm
flush for tlb range flushes (which will happen right before
flush_pgtables is called), whereas on sparc64 we do a more finegrained
tlb flush for ranges which won't take care of the virtual page table
mappings used by the TLB miss scheme.
Point taken. #2 means nothing would be gained. (Unless clearing a
whole page is faster than clearing one pte at a time..)
Clearing a whole page is faster on UltraSparc, because it would use
the high speed VIS block memory stores which avoid cache pollution.
Similar tricks could be done on the modern Pentiums...
Later,
David S. Miller
davem@redhat.com
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