>
> root@chaos.analogic.com said:
> > You do not swap to timer channel 0, you need the highest priority
> > interrupt for the main timer.
>
> You can reprogram the priorities.
>
The priorities are only programable relative to which per-controller
interrupt has the highest priority. The CMOS timer is hard-wired to
IRQ8, which is already the highest priority for the second (cascaded)
controller. To make this assembly the highest priority, you would
need to make IRQ2, the cascade, the highest priority. This means that
IRQ1 (the keyboard --also hardwired) would become the lowest priority.
Further, given this, the IRQ you want to steal, IRQ0, becomes the next
lowest priority in the system. In PCI/SMP machines, where you use
the APIC chip, this gets even further from reality because the CMOS
timer doesn't even get there.
As I said, you do not swap to timer channel zero.
There is, furthermore, no reason to do so. The fact that the original
inquiry was about an ADC that "ran" at 70 kHz, means nothing about
the speed at which it was expected to interrupt. In fact, the
maximum rate at which you can interrupt Linux, and record that an
interrupt occurred in your ISR (nothing else), is almost, but not
quite, 50 kHz on a dual pentium running 400 MHz with a 100 Mhz main
bus. I have a device-driver module which does little more than measure
these kinds of things if you are interested.
Cheers,
Dick Johnson
***** FILE SYSTEM WAS MODIFIED *****
Penguin : Linux version 2.2.6 on an i686 machine (400.59 BogoMips).
Warning : It's hard to remain at the trailing edge of technology.
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