Yes, so ? For quite a while so called "Super Scalar" tricks
in "IPIC" (Implicitely ..) are delivering multiple instructions
per single clock cycle. EPIC in itself does not give you
anything special, likely it will cause more constraints to
the COMPILER, e.g. results of some calculation must be used
only after given delay of so and so many instructions so that
they arrive thru the computing pipeline back into registers.
(Because e.g. 6 step pipeline would mean terrible delays and
computing inefficiency, things can't be done quite that way,
which means that Merced will need all possible tricks out of
the books, including register renaming, shadowing, etc, which
are now in use in high-performance RISC processors including
Alphas, MIPSes, and UltraSPARCs. (PowerPC also, very likely.))
Super Scalar IPICs are now doing 3 to 6 instructions per clock
cycle. If Merced is to be even comparable, it can't do it with
two instructions per instruction word.
At the DSP world there have been EPIC style instruction sets
around for at least 10 years. Single instructions can do
Multiply-Accumulate + two memory to register moves + address
register calculations for each memory pointer registers.
(Agreeably that case is rather special one, but anyway..)
In research community things known as VLIW (Very Long Instruction
Word) are known for quite a while, but aside of learning new
things at the compiler writing (which does benefit both EPIC
and Super Scalar IPIC processors), they haven't been commercial
successes.
> I was wondering if there were any plans on supporting that technique in
> the Linux kernel-world, and if so, if there are any sites where more
> info could be found. I searched the archives of the list, but I found no
> references to any addresses, or even if the project existed.
There is an effort of porting Linux to Merced underway, but
to learn any salient details of it, you have to sign NDA.
(Until the Merced is published.)
> If not, I think it might be worth considering taking this new technique
> into the 2.3.x kernel series.
Processor instruction set encoding style is not a technique
in kernel sense.
> Greetings,
> Nils Vogels.
/Matti Aarnio <matti.aarnio@sonera.fi>
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