Software TLB MMU's are nice because you're not locked to a certain page
hierarchy structure. But you still have to translate the kernel through
the TLB, unless there is some additional segmenting or "hack" somewhere,
like special PTE's with huge spans (like the 4MB on Intel), as you note.
Hm come to think of it, how can the phys memory be mapped at c0000000 on
the Intel - what happens if you have more than 1 gig phys mem and a
process goes inside the kernel and needs to adress physical pages ? Or
maybe intel linux doesn't support more than 1 gig phys ram.
I guess some coarse form of segmenting in the MMU (before TLB lookup)
would be ideal for doing the kernel phys mapping, reducing TLB trashing.
/Bjorn
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