>In order to make things right, the driver writers/maintainers must be
>carefull about the order of operations each time this is required.
>For that to be achieved, all the parts that may buffer data, and so
>reorder operations, must be considered. The C compiler, the CPU, the host
>bridge, inter-bus bridges and the PCI device are the parts I am talking
>about.
Yes, but this can quickly become a real nightmare. Event on PCI, ordering
rules can change from one platform to another, from one PCI chipset to
another, etc...
There are lots of drivers who don't really need the very best
performances out of the bridge path, possibly because most actual data
transfer is done in DMA and the only few i/os are only necessary to setup
the DMA descriptors, or simply because the device is a really simple one.
In all those cases, handling all the different ordering rules of all the
different platforms and busses becomes a challenge that would prevent
lots of people from even trying to write a driver ;-)
That's why I like the idea of having simple, CPU-ordered readl/writel
(driver writer still need to take care of write posting done by the
various bridges, as it has always been the case, and as it was, I think,
never correctly handled in most drivers).
P.S. A question: As far as PCI write posting is concerned, is it
_guaranteed_ that a read to the same bus range will flush any outstanding
writes to the same range or is it simply a common practice of PCI bridges ?
--
Perso. e-mail: <mailto:bh40@calva.net>
Work e-mail: <mailto:benh@mipsys.com>
BenH. Web : <http://calvaweb.calvacom.fr/bh40/>
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