I'm still confused. PCI is cache-coherent w.r.t. DMA by the spec,
but not on UltraSparcs, and maybe not sometimes on Cyrix. It doesn't
define memory ordering - the most common platform is strictly ordered,
while others (UltraSparc, yet again) have selectable looser ordering.
The address space is sparse for non-word access on Alphas, and non-sparse
in all other cases that I know. Although it defines separate IO and
memory spaces, the IO space will be memory mapped on most platform
types. (It could be on the x86, as well, if someone insane enough made
a chipset to do it...)
As far as I can tell, SBus and NuBus are subsets of these possible
semantics. The biggest difference I can think of, compared to PCI/ISA/
MCA/EISA, is that they both have well-defined per-card config ROM specs,
and the per-slot address spaces in NuBus. (or do you mean that SBus
and NuBus have much stricter semantics, and so should not fall in the
PCI framework?)
For that matter, I don't think cache coherency affects readl/writel
semantics - it affects the sequence of actions a driver must take to
ensure that the CPU reads the correct value out of *motherboard* memory,
not over the bus. The non-endian stuff that's been kicked around in this
thread has mostly been memory ordering and barriers, not cache coherency.
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