On Sep 29, 11:33am, William Lash wrote:
> ....
> Anyway, I find that the interrupt is entered due to a BUSFREE
> indication in the interrupt status register. The ISR goes down, and
> calls phaseBusFree(), presumably to handle that condition, but the bit
> never seems to get cleared in the interrupt status register.
>
> Of course, the interesting question is, "Why does this only show up
> with a faster processor?". There seem to be 2 possibilities, either
> the faster processor causes the original BUSFREE interrupt to occur in
> such a way that the normal BUSFREE handling can't clear it, or that the
> faster processor makes it so that the code that is supposed to clear
> the BUSFREE condition doesn't work correctly.
>
>
> Anyway, attached below are the patch that I used to gather data, and
> the logged results from mounting the CD several times. The patch
> contains code to detect other conditions in the ISR that I thought
> might cause problems as well. Any ideas about what to try would be
> appreciated. I will forward a copy of this to mylex tech support
> as well. It looks like the FlashPoint.c file is basically some code
> from their development kit.
> .....
Thanks for the patch!!!
I finally got time to apply it this weekend, and plugged my FlashPoint
back in, and it seems to be working like a charm. I should check for
the reset messages to see if it's having to do this stuff, but I
suspect that it is, because without the patch, I usually couldn't even
get the system to *BOOT* with the FlashPoint installed.
Just my $.02 worth...
-Nick
--
+-------------------------------+--------------------------------------------+
| /`--_ Nicholas R LeRoy | In a world without fences, Who needs Gates?|
|{ }/ Norland Corporation | ---- Experience Linux! ---- |
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| nick.leroy@norland.com | #include <disclaimer.h> |
|http://www3.norland.com/~nleroy| These are my own ideas, not my employer's. |
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