Re: spin_unlock optimization(i386)

Gerard Roudier (groudier@club-internet.fr)
Thu, 25 Nov 1999 22:29:45 +0100 (MET)

On Wed, 24 Nov 1999, Erich Boleyn wrote:

> [I'm writing from my home system now...]
>
> Andrea Arcangeli <andrea@suse.de> wrote:
>
> > ... In most cases the only thing we care is the order of
> > _reads_ and of _writes_. Nothing more. It seems by reading your email that
> > we are wasting time adding explicit memory barriers with lock on the bus
> > to enforce ordering on IA32. So I believe we can remove them as the
> > hardware is enforcing ordering for us.
>
> I believe so.

If something as simple as the following rule had been written in the
Intel doc:

- CPU2 will never see a STORE from CPU1 pass a LOAD from CPU1.

(May-be STORE and LOAD are misplaced, but the right rule should not be
more complex, in my opinion that had been confused by the current Intel
docs)

Then, given that the 'processor ordering' of WRITEs is clearly documented,
no confusion would have been possible, this thread would never have
happenned and may-be Linux would never have been broken for SMP locks.

So, I suggest Intel to _asap_ fix their documentation accordingly, so that
people will not have to beleive any more but just will be allowed to
understand how ordering actually work for IA32 from the docs.

Just my $0.00

Gérard.

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