> CPU0 CPU1
>
>volatile int i, __fill[8], j; int a, b;
>
> i = j = 0;
>
> for (;;) { for (;;) {
> i++; a = i;
> j++; b = j;
> } if (a < b)
> BUG()
> }
>
>(i and j are shared common variables on different cachelines, a and b are
>local ones)
>
>if your theory is true, then 'BUG()' should trigger sooner or later,
>correct?
Your causality.c program attached in your other email (and described the
design above) is buggy and says nothing about Weak ordering in SMP.
This is what happens and that's why it obviously fails immediatly:
CASE 1:
CPU0 CPU1 state of memory and registers
---- ---- -----------------------------
i=0 j=0 a=? b=?
a=i i=0 j=0 a=0 b=?
i++ i=1 j=0 a=0 b=?
j++ i=1 j=1 a=0 b=?
b=j i=1 j=1 a=0 b=1
a < b -> BUG()
CASE 2:
CPU0 CPU1 state of memory and registers
---- ---- -----------------------------
i=0 j=0 a=? b=?
i++ i=1 j=0 a=? b=?
a=i i=1 j=0 a=1 b=?
b=j i=1 j=0 a=1 b=0
j++ i=1 j=1 a=1 b=0
a > b -> you seems to like this
result
As you can see the reader can see a<b or a>b depending on the timings. The
fact a>b or b>a tells nothing about the ordering of the reads. So you have
_not_ provided the proof the IA32 SMP WB is using Weak ordering.
Tomorrow I'll check Manfred's proggy (now it's getting too late...).
Andrea
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