By the way, this is the wording of 'Intel docs'. ;-)
They wrote 'flush to memory', but one must understand 'flush to cache (or
memory)' for the reason that when a STORE goes to the cache then memory
coherency is maintained by the cache protocol among processors.
Sorry for the misunderstanding. I _obviously_ meant flush to cache and
also had in mind this wording and nothing else.
By the way, I _maintain_ my remark (with the wording fix) since
serialization may be used to flush write buffers to cache for other
processors to be aware of writes.
> as anywhere else.
Gérard.
PS: PCI appears less relevant that a Christmas Tree in this context
given the subject of this thread. ;-)
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