Re: [PATCH 3/5] perf, x86: Disable PEBS on clowertown chips
From: Peter Zijlstra
Date: Fri Mar 05 2010 - 16:05:43 EST
On Fri, 2010-03-05 at 20:15 +0100, Peter Zijlstra wrote:
> On Fri, 2010-03-05 at 10:58 -0800, Stephane Eranian wrote:
> > > case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
> > > + x86_pmu.quirks = intel_clowertown_quirks;
> > That's too coarse grain!
> > It is more subtle than this. Some of the errata are marked as Plan
> > fix. They seem to be
> > fixed in later models. Your looking at the E5xxx series errata but the
> > E7xxx do not have
> > the same problems.
> OK, I'll look at those errata again and try to come up with a stepping
> test for this errata.
The two serious ones, AJ106 and AJ68 are no fix and are listed as such
in all errata I can find, including the 700 series.
I checked the 65nm Core2Duo, Xeon 5200 and Xeon 700 spec updates.
Going by that it seems the full model 15 family is broken and I'll leave
the patch as is.
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