Re: PCI-E Link training bug

[Valdis . Kletnieks]

On Tue, 03 Aug 2010 00:36:35 -1000, Jeff Roberson said:

> At least one intel chipset will occasionally negotiate a 4x link for an 8x 
> device in an 8x port.  It is a known errata in the 5400 mch.  

Can this get wrapped in some sort of 'if (chipset == MCH5400)'?  There's no
sense in adding an entire second of delay going around this loop 4 times when
it's a valid config on a non-5400 chipset.

Attachment: pgp00000.pgp
Description: PGP signature