On Fri, 2011-05-20 at 12:08 +1000, Benjamin Herrenschmidt wrote:Right, L1D is coherent if write throug is set.
On Thu, 2011-05-19 at 20:32 -0500, Kazutomo Yoshii wrote:Hrm... looking at the doco you pointed me to, it looks like the L1 -is-
Actually DMA sends invalidate requests to the snoop unit(L2 level).Well, some other 44x also have a snooping L2 (more or less), but L1 is
BGP SoC is a bit different from other 4xx base.
usually the problem.
coherent, it gets snoop kills from the L2.
Ok so we do need to make this non-coherent cache stuff a runtime optionWhat sort of runtime option do you mean?
(well, we need that for 440+476 too anyways so may as well do it now).
As for the alignment of kmalloc, it looks like a hack that should be
done in the torus code itself.
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