Re: [PATCH 1/11] ARM: tegra: add function to control the GPU rail clamp

From: Lucas Stach
Date: Tue Dec 30 2014 - 11:42:43 EST

Am Montag, den 29.12.2014, 10:49 +0800 schrieb Vince Hsu:


> >> That's a read fence to assure the post of the previous writes through
> >> Tegra interconnect. (copy-paster from
> >>
> > I see what it does, the question is more about why this is needed.
> > What is the Tegra interconnect? According to the TRM the Tegra contains
> > some standard AXI <-> AHB <-> APB bridges. That a read is needed to
> > assure the write is posted to the APB bus seems to imply that there is
> > some write buffering in one of those bridges. Can we get this documented
> > somewhere?
> The TRM does mention a read after the write. Check the section
Unfortunately this doesn't seem to be included in the public TRM. It
would be nice if this could be documented either in the next version of
the TRM or as a public Appnote.


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