Re: [PATCH v2 5/5] dt-bindings: PCI: add support for new generation controller
From: Bjorn Helgaas
Date: Thu Aug 03 2017 - 18:45:22 EST
On Thu, Jul 27, 2017 at 10:58:39AM +0800, honghui.zhang@xxxxxxxxxxxx wrote:
> From: Ryder Lee <ryder.lee@xxxxxxxxxxxx>
> Add support for MediaTek new generation controller and update related
> Signed-off-by: Ryder Lee <ryder.lee@xxxxxxxxxxxx>
> Signed-off-by: Honghui Zhang <honghui.zhang@xxxxxxxxxxxx>
> .../devicetree/bindings/pci/mediatek-pcie.txt | 168 ++++++++++++++++++++-
> 1 file changed, 161 insertions(+), 7 deletions(-)
> diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
> index a968f25..179329b 100644
> --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
> @@ -3,18 +3,31 @@ MediaTek Gen2 PCIe controller
> Required properties:
> - compatible: Should contain one of the following string:
> + "mediatek,mt2712-pcie"
> + "mediatek,mt7622-pcie"
> - device_type: Must be "pci"
> -- reg: Base addresses and lengths of the PCIe controller.
> +- reg: Base addresses and lengths of the PICe subsys and root ports.
> +- reg-names: Names of the above areas to use during resource look-up.
> - #address-cells: Address representation for root ports (must be 3)
> - #size-cells: Size representation for root ports (must be 2)
> - clocks: Must contain an entry for each entry in clock-names.
> See ../clocks/clock-bindings.txt for details.
> -- clock-names: Must include the following entries:
> - - free_ck :for reference clock of PCIe subsys
> - - sys_ck0 :for clock of Port0
> - - sys_ck1 :for clock of Port1
> - - sys_ck2 :for clock of Port2
> +- clock-names:
> + Mandatory entries:
> + - sys_ckN :transaction layer and data link layer clock
> + Required entries for MT2701/MT7623:
> + - free_ck :for reference clock of PCIe subsys
> + Required entries for MT2712/MT7622:
> + - ahb_ckN :AHB slave interface operating clock for CSR access and RC
> + initiated MMIO access
> + Required entries for MT7622:
> + - axi_ckN :application layer MMIO channel operating clock
> + - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
> + pcie_mac_ck/pcie_pipe_ck is turned off
> + - obff_ckN :OBFF functional block operating clock
> + - pipe_ckN :LTSSM and phy/mac layer operating clock
> + where N starting from 0 to the maximum number of root ports.
Probably to "one less than the number of root ports"?