[PATCH v2 0/3] coresight: Add barrier packet when moving offset forward
From: Mathieu Poirier
Date: Mon Aug 26 2019 - 15:46:09 EST
This set builds on top of an original patch by Yabin Cui that deals with
cases where the ETR buffer it bigger than the space available in the perf
ring buffer. The work herein complements Yabin's by inserting barrier
packets after the head of the memory buffer has been moved forward in order
for the trace decoder to still synchronise with the trace stream.
Applies cleanly to the coresight next branch.
New to V2:
- Added Yabin's Tested-by.
- Addressed Leo's comment about extending the solution to the sysfs
- Split the work in 3 patches rather than 2.
Mathieu Poirier (3):
coresight: tmc: Make memory width mask computation into a function
coresight: tmc-etr: Decouple buffer sync and barrier packet insertion
coresight: tmc-etr: Add barrier packets when moving offset forward
.../hwtracing/coresight/coresight-tmc-etf.c | 23 +--------
.../hwtracing/coresight/coresight-tmc-etr.c | 47 ++++++++++++++-----
drivers/hwtracing/coresight/coresight-tmc.c | 28 +++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
4 files changed, 67 insertions(+), 32 deletions(-)