[PATCH RFC v2 00/14] Support wakeup capable GPIOs

From: Lina Iyer
Date: Fri Sep 13 2019 - 18:00:32 EST

Thanks for all the helpful reviews. Here is the next revision addressing the

Changes in RFC v2:
- Address review comments #3, #4, #6, #7, #8, #9, #10
- Rebased on top of linux-next GPIO latest patches [1],[3],[4]
- Increase PDC max irqs in #2 (avoid merge conflicts with downstream)
- Add Reviewed-by #5

Note: This revision does not update writing the config registers that are
written from the PDC. There needs more discussion in that area. #6, #7


This series is another attempt on adding wakeup capable GPIOs for QCOM
SoC. This patchset is based on Linus's support for hierarchical GPIOs
merged into linux-next [1]. The essense of the idea remains the same as
the previous submission [2]. GPIO irqchip TLMM is setup in hierarchy wit
the PDC as the wakeup-parent. PDC's interrupt parent is the GIC. GPIOs
in QCOM SoC that are wakeup capable (when TLMM is powered off) are
routed to the PDC as well and can be detected at the always-on interrupt
controller (PDC). The idea is setup the irqchips in hierarchy and if the
interrupt is handled at the PDC, then TLMM relinquishes control and
configuration of the interrupt to the PDC.

There are few new additions in this submission. The first is the
additional SPI configuration that needs to be done to setup the GPIO
type in a register interface between the PDC and the GIC. This is needed
only for GPIOs. This registers in some QCOM SoCs is access restricted
and has to be written from the TZ. The DT bindings are also updated for
this new requirement. The second change is that with the new
hierarchical support in gpiolib, we could remove the .alloc and
.translate functions from the pinctrl driver. But to distinguish the
case where a wakeup interrupt controller needs the TLMM to configure the
GPIO interrupts (in the case of MPM interrupt controller), irqdomain
flags have been added. The third change is ensure the interrupt
controllers' interrupt pending bits are cleared when the GPIO is enabled
as an interrupt.

Please consider reviewing these patches.


[1]. https://lore.kernel.org/linux-gpio/20190808123242.5359-1-linus.walleij@xxxxxxxxxx/
[2]. https://lkml.org/lkml/2019/5/7/1173
[3]. https://lore.kernel.org/r/20190819084904.30027-1-linus.walleij@xxxxxxxxxx
[4]. https://lore.kernel.org/r/20190724083828.7496-1-linus.walleij@xxxxxxxxxx

Lina Iyer (12):
irqdomain: add bus token DOMAIN_BUS_WAKEUP
drivers: irqchip: qcom-pdc: update max PDC interrupts
drivers: irqchip: pdc: Do not toggle IRQ_ENABLE during mask/unmask
drivers: irqchip: add PDC irqdomain for wakeup capable GPIOs
of: irq: document properties for wakeup interrupt parent
dt-bindings/interrupt-controller: pdc: add SPI config register
drivers: irqchip: pdc: additionally set type in SPI config registers
drivers: pinctrl: msm: setup GPIO chip in hierarchy
drivers: pinctrl: sdm845: add PDC wakeup interrupt map for GPIOs
arm64: dts: qcom: add PDC interrupt controller for SDM845
arm64: dts: qcom: setup PDC as the wakeup parent for TLMM on SDM845
arm64: defconfig: enable PDC interrupt controller for Qualcomm SDM845

Maulik Shah (2):
genirq: Introduce irq_chip_get/set_parent_state calls
drivers: irqchip: pdc: Add irqchip set/get state calls

.../bindings/interrupt-controller/interrupts.txt | 13 ++
.../bindings/interrupt-controller/qcom,pdc.txt | 13 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 +
arch/arm64/configs/defconfig | 1 +
drivers/irqchip/qcom-pdc.c | 238 +++++++++++++++++++--
drivers/pinctrl/qcom/pinctrl-msm.c | 119 +++++++++++
drivers/pinctrl/qcom/pinctrl-msm.h | 16 ++
drivers/pinctrl/qcom/pinctrl-sdm845.c | 23 +-
include/linux/irq.h | 6 +
include/linux/irqdomain.h | 1 +
include/linux/soc/qcom/irq.h | 32 +++
kernel/irq/chip.c | 44 ++++
12 files changed, 502 insertions(+), 15 deletions(-)
create mode 100644 include/linux/soc/qcom/irq.h

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