Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board
From: Takashi Iwai
Date: Mon Aug 03 2020 - 12:56:37 EST
On Mon, 03 Aug 2020 18:45:29 +0200,
Lu, Brent wrote:
> > > Hi Takashi,
> > >
> > > I've double checked with google. It's a must for Chromebooks due to
> > > low latency use case.
> > I wonder if there's a misunderstanding here?
> > I believe Takashi's question was "is this a must to ONLY accept 240 samples
> > for the period size", there was no pushback on the value itself.
> > Are those boards broken with e.g. 960 samples?
> I've added google people to discuss directly.
> Hi Yuhsuan,
> Would you explain why CRAS needs to use such short period size? Thanks.
For avoid further misunderstanding: it's fine that CRAS *uses* such a
short period. It's often required for achieving a short latency.
However, the question is whether the driver can set *only* this value
for making it working. IOW, if we don't have this constraint, what
actually happens? If the driver gives the period size alignment,
wouldn't CRAS choose 240?