Re: [PATCH v2 00/14] HSI2, UFS & UFS phy support for Tensor GS101

[Krzysztof Kozlowski]

On 23/04/2024 22:49, Peter Griffin wrote:
> Hi James, Martin, Alim, Bart, Krzysztof, Vinod, all
> 
> Firstly, many thanks to everyone who reviewed and tested v1.
> 
> This series adds support for the High Speed Interface (HSI) 2 clock
> management unit, UFS controller and UFS phy calibration/tuning for GS101
> found in Pixel 6.
> 
> With this series applied, UFS is now functional on gs101. The SKhynix
> HN8T05BZGKX015 can be enumerated, partitions mounted etc. This allows us to
> move away from the initramfs rootfs we have been using for development so far.
> 
> Merge Strategy
> 1) UFS driver/bindings via UFS/SCSI tree (James / Martin / Alim)
> 2) GS101 DTS/DTSI should go via Krzysztofs Exynos SoC tree
> 3) Clock driver/bindings via Clock tree (Krzysztof / Stephen)
> 4) PHY driver/bindings via PHY tree (Vinod)
> 
> The v2 series has been rebased on next-20240422, as such all the phy parts
> which were already queued by Vinod have been dropped. Two new phy patches
> are added to address review feedback received after the patches were queued.
> 
> The series is broadly split into the following parts:
> 1) dt-bindings documentation updates
> 2) gs101/oriole dts & dtsi updates
> 3) Prepatory patches for ufs-exynos driver
> 4) GS101 ufs-exynos support
> 5) gs101 phy fixes
> 

I asked to split, otherwise please explain why PHY and UFS depends on
DTS and clk.

Best regards,
Krzysztof