> On 16 Apr 96 at 2:56, Howard C. Tyler wrote:
>
> ---snip---
> > Attached is a patch, against 1.3.86, that leaves CD and
> > NW bits they way bios set them. The patch also enhances the
> > right-ctl+srool-lock display to show the value of cr0. If cr0
> > is 0x8xxx xxxx, L1 caching is enabled, if cr0 is 0xExxx xxxx,
> > L1 is disabled.
> > I suspect that caching and the newer 486 cpu's are the
> > source of some of the strange OOPS's. YMMV ;-)
>
> Good work! What about "yais" (yet another init string) like
> "cpuflags=", or "cachecontrol="?
>
> >
> > Howard
> >
> OK!
>
> Ulrich
>
Setting up a motherboard's L2 cache and bus(s) interface(s) is a
highly technical task, best reserved for the board's designer. Bios
should deliver control of the CPU with cr0's CD and NW's bits set
appropriately for what ever you've configured bios. An ioctl call
might be useful for tinkering, but in general, I think linux should
maintain these bits just as they are delivered.
Note, 80386 processors don't have these bits, Cyrix 486's define them
differently, and I have no idea what Pentium, et. al. think of these
bits.
Howard
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Howard C. Tyler | email: theurgi@primenet.com
phn: (602)-866-9074 | 1KSPT: 13.96 exCOG 1741
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