Re: mmx support with smp

Ricky Beam (
Wed, 9 Jul 1997 09:46:51 -0400 (EDT)

Letting the chips fall where they may, I quote Jeremy A. Gilbert:
> I belive that since the MMX registers are overlayed over the
>FPUs floating point registers, any OS which properly performs context
>switching for the FPU will support MMX by default. This was probably a
>neccesary design aspect for Intel, since it seems to have made a definate
>commitment towards backward compatability. (If they were gonna add more
>registers, they might as well add more general purpose ones to.)

But isn't there some other things going on insode the CPU re: FPU/MMX use?
If you context switch a task off a processor the is using MMX, then load
any other process expecting FPU setup...

As I remember, there is a price (a heavy one) for switching back and forth
between MMX and FPU usage. The kernel may not be able to tell what mode
the application has put the CPU in. We shall see, I'm sure.

(Doesn't the Tyan Tomcat III support two 166-MMX processors? All I remember
is the power warnings -- MMX processors draw more power than the non-MMX
cousins which causes problems for the Tomcat's as they were designed before
there was such a thing.)