Re: Cyrix 6x86MX and Centaur C6 CPUs in 2.1.102

Phil's Kernel Account (kernel@eiterra.nls.net)
Mon, 18 May 1998 13:21:58 -0400 (EDT)


On Mon, 18 May 1998, [ISO-8859-1] André Derrick Balsa wrote:

#I have a question. The 6x86MX allows one to lock L1 cache lines. Would
#it be interesting to group some kernel variables and keep them in the L1
#cache? Would that increase the kernel performance during context
#switches?

*blinkblink* Okay, I'm going to let pine sit here till AFTER I'm a bit
more awake.. :)

First off, YES. You *CAN* lock L1 cache lines. I personally don't suggest
it, but you can do it. And you probably could, it probably would.
Especially since the Cx6x86MX has, IIRC, 64K of unified. (It MAY be 128K,
I'm not sure. I *AM* positive it's unified. ALL Cx6x86's and up have had
unified L1 cache. MUCH faster than block addressing.:)

#Please give me a hint of which data structures could be kept in the L1
#cache, and their size.

Uh, Alan? Linus? Hints?
Don't look at me! I just know the CPUs! ;)

-Phil R. Jaenke (kernel@nls.net / prj@nls.net)
TheGuyInCharge(tm), Ketyra Designs - We get paid to break stuff :)
Linux pkrea.ketyra.INT 2.0.33 #15 Sat Apr 18 00:40:21 EDT 1998 i586
Linux eiterra.nls.net 2.0.33 #15 Fri Apr 17 00:22:13 EDT 1998 i586
- Linus says for 'brave people only.' I say 'keep a backup.' - :)

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