Re: Locking L1 cache lines in Cyrix 6x86MX CPUs
Tue, 19 May 1998 14:01:53 +0200

On Tue, May 19, 1998 at 10:24:43AM +0100, Mike Jagdis wrote:

> My own feeling is that this is not so useful as it might appear
> at first glance. If you _really_ want to try something interesting
> why not write a gcc back end that uses a locked L1 line as a nice
> big register file and see if you can push the x86 architecture to
> new heights?

... which somehow reminds of the Texas Instruments TMS 8900 used in the
TI99/4a, just that it had no cache and the register file was part of the
memory. Slow, especially when the memory bus is shared with the video

Playing games with the cache is almost always a bad idea. The standard
lru or lru like replacement algorithems tend to be pretty good heuristics.
The cache locking feature is usually a candy added for sake of ``ultra
hard realtime'' apps for which cache line replacement would cause too much
jitter in the reaction times. Before that these guys often used to live
without caches for sake of consistent memory delays.


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