Re: Locking L1 cache lines in Cyrix 6x86MX CPUs

Michael Meissner (
Tue, 19 May 1998 19:29:27 -0400

| If we lock 1Kb of L1 cache lines, and use these adresses just as if they
| were a uniform set of 256 32-bit registers, do you think this would
| improve the performance of the code generated by gcc?

They are still memory references as far as the ISA is concerned. Since the
i386 is a 1 1/2 address machine (ie, one address can be memory, but the other
has to be a register), you still will need to move things to/from the ISA
registers (which given the specialized nature tend to be reload registers in
complex functions).

Obviously to use this, you will need to rebuild all of your favorite apps
(unless you are talking kernel only) with your special compiler option. You
also need to have the context code swap these values as well.

I am skeptical it will provide much benefit.

| The compiler would just see them as R1-R256 and would have a homogeneous
| instruction set relative to these R1-R256 (a very large subset of the
| standard X86 instruction set).
| These pseudo-register instructions would have the same CPU clock cycle
| count as standard register instructions.

Nope, they would have the same CPU clock cycle as standard memory references
that hit the L1 cache.

| Regards,
| ------------------------
| André Balsa

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