Re: Locking L1 cache lines in Cyrix 6x86MX CPUs

=?ISO-8859-1?Q?Andr=E9?= Derrick Balsa (
Wed, 20 May 1998 20:58:26 -0100

Hi Michael,

Michael Meissner wrote:
> | As far as I know, register allocation is done at the end of the global
> | optimization pass, just before code generation, using a technique called
> | graph coloring - which works best when the CPU has at least 16 registers
> | available, obviously not the case with x86 machines.
> Not really. After register allocation is the second scheduling pass, the
> delayed branch pass, peephole support and then emitting the assembler code. In
> addition, GCC does NOT use graph coloring for register allocation (that method
> is patented by IBM).

You are referred to the following DejaNews link:

André Balsa

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