Re: IDE-Driver Update :: Testing Requested (Ultra33 as RAID?? (fwd))

Andre M. Hedrick (hedrick@astro.dyer.vanderbilt.edu)
Tue, 25 Aug 1998 08:06:53 -0500 (CDT)


On Tue, 25 Aug 1998, Martin Mares wrote:

> > 00:0e.0 RAID bus controller: Promise Technology, Inc. 20246 (rev 01)
> > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> > ParErr- Stepping- SERR- FastB2B-
> > Status: 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
> > <TAbort- <MAbort- >SERR- <PERR-
> > Latency: 64 set
> > Interrupt: pin A routed to IRQ 11
> > Region 0: I/O ports at fff0
> > Region 1: I/O ports at ffe4
> > Region 2: I/O ports at ffa8
> > Region 3: I/O ports at fbe4
> > Region 4: I/O ports at ff80
> > Expansion ROM at ffbe0000
> > 00: 5a 10 33 4d 07 00 00 02 01 00 04 01 00 40 00 00
> > 10: f1 ff 00 00 e5 ff 00 00 a9 ff 00 00 e5 fb 00 00
> > 20: 81 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > 30: 01 00 be ff 00 00 00 00 00 00 00 00 0b 01 00 00
> > 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > 50: ee 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > 60: f5 6c 43 00 c4 f3 4f 00 f9 13 40 00 c4 f3 4f 00
> > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > 80: 5a 10 33 4d 07 00 00 02 01 00 04 01 00 40 00 00
> > 90: f1 ff 00 00 e5 ff 00 00 a9 ff 00 00 e5 fb 00 00
> > a0: 81 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > b0: 01 00 be ff 00 00 00 00 00 00 00 00 0b 01 00 00
> > c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > d0: ee 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > e0: f5 6c 43 00 c4 f3 4f 00 f9 13 40 00 c4 f3 4f 00
> > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>
> Both halves of the configuration space are _identical_, therefore the
> second copy not only uses the same IRQ, but also maps to the same addresses.
> How do you talk with the second controller?

I don't know, but with close examination of pcb-lanes, each hwif looks to
be assigned a controller.

I agree that "Both halves of the configuration space are _identical_";
however, on two or three occassions, it has reported two different
interrupt values. With this in mind, I felt it was needed to prevent
a potential crash with two interrupt being passed to the same card.

Again these are anomolies that have been observed, and have crashed a
system at the same rate of appearance.

Cheers,
Andre

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