Gerard> On Sun, 15 Nov 1998, Jakub Jelinek wrote:
>> > I heard of a 133 MHz PCI BUS project. In 64 bit mode, the total
>> bandwidth > will be 53.2 GB/sec. Perhaps future Java Systems would
>> need such a memory > bandwidth ;-). > The SUN method to enhance
>> computing seems worse than Intel/M$$ one to me > in some aspects.
>>
>> I don't know how can you use on a single PCI bus 64 PCI devices,
>> nor find it easy to build a large system where you can mix buses
>> (have 10 boards PCI and 5 boards with other bus type), not counting
>> that the backbone bus in the Enterprise servers is IMHO superior to
>> PCI (256bit packet switched bus).
Gerard> My concern was an unified address mapping to be the only
Gerard> acceptable solution since other scheme leads to kind of
Gerard> complexity I donnot want to deal with from software. You may
Gerard> love SUN stuff for personnal reasons but I donnot like their
Gerard> BUSes addressing model for software technical reasons.
Add a bus-key to the virt/phys conversion functions and you are all
set. In fact it would solve a lot of problems for the m68k port (and
possibly others) if they inb/outb macros people tend to use in lotsa
drivers required a bus-key or a base offset (which could be the same
thing) as some systems use mmap'ed I/O for both ISA and PCI busses'
I/O space in the same machine, but without having them at the same
address.
Gerard> BTW, it is the PCI BUS architecture that won the approbation
Gerard> of most manufacturers and not the SUN approach for BUSes. You
Gerard> seem to forget that a good standard must also allow to make
Gerard> superior goods for a minimal cost.
PCI bus won because it was far better than what was available in PC's
before. However, PCI is SLOW and we are beginning to suffer from this
now. Intel chose to create this ridiculous AGP crap instead of putting
real PCI 64/66 in their machines, however even that is relatively slow
and it is extremely rare in PCs.
>> BTW: I don't know much about 133MHz PCI project, but simple math
>> tells me it probably is not either 64bit, or runs much faster, as
>> 133MHz x 8B = 1.03GB/sec.
Gerard> I just pointed out as irrelevant David's remarks seemed to me.
Gerard> 100 BUSes x 1.03 GB/s = 103 GB/s. Sorry for my mistake that
Gerard> just lowered the actual bandwidth to half its theorical value.
It's not the issue, btw. DEC has such systems as well. However on some
architectures you map the bus to the memory/CPU when you need it and
unmap it again after a DMA operation.
Jes
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