> > I heard of a 133 MHz PCI BUS project. In 64 bit mode, the total bandwidth
> > will be 53.2 GB/sec. Perhaps future Java Systems would need such a memory
> > bandwidth ;-).
> > The SUN method to enhance computing seems worse than Intel/M$$ one to me
> > in some aspects.
>
> I don't know how can you use on a single PCI bus 64 PCI devices, nor find it
> easy to build a large system where you can mix buses (have 10 boards PCI and
> 5 boards with other bus type), not counting that the backbone bus in the
> Enterprise servers is IMHO superior to PCI (256bit packet switched bus).
My concern was an unified address mapping to be the only acceptable
solution since other scheme leads to kind of complexity I donnot want to
deal with from software. You may love SUN stuff for personnal reasons but
I donnot like their BUSes addressing model for software technical reasons.
BTW, it is the PCI BUS architecture that won the approbation of most
manufacturers and not the SUN approach for BUSes. You seem to forget that
a good standard must also allow to make superior goods for a minimal
cost.
If you have 64 bit architecture and only 40 address lines, even if you are
using 1GB space for each BUS mapping, you will only lose 100 GB space
using an unified address mapping which represents only 10% of the total
physical address space. So why using offsets, bitmasks or whatever address
bits tampering in order to address to/from BUS spaces?
> BTW: I don't know much about 133MHz PCI project, but simple math tells me it
> probably is not either 64bit, or runs much faster, as 133MHz x 8B = 1.03GB/sec.
I just pointed out as irrelevant David's remarks seemed to me.
100 BUSes x 1.03 GB/s = 103 GB/s.
Sorry for my mistake that just lowered the actual bandwidth to half its
theorical value.
Regards,
Gerard.
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