Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox

[Konrad Dybcio]

On 9/25/25 8:32 AM, Pankaj Patil wrote:
> From: Sibi Sankar <sibi.sankar@xxxxxxxxxxxxxxxx>
> 
> Enable pdp0 mailbox node on Glymur SoCs.
> 
> Signed-off-by: Sibi Sankar <sibi.sankar@xxxxxxxxxxxxxxxx>
> Signed-off-by: Pankaj Patil <pankaj.patil@xxxxxxxxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -4065,6 +4065,14 @@ watchdog@17600000 {
>  			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
>  		};
>  
> +		pdp0_mbox: mailbox@17610000 {
> +			compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
> +			reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;

1 a line, please

> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

I see this has 3 channels, with 3 separate IRQs (but one pair of address
spaces) - should we extend this description?

> +			#mbox-cells = <1>;
> +			qcom,rx-chans = <0x7>;

This further seems to confirm what I found (BIT(0) | BIT(1) | BIT(2) == 0x7)
however this property doesn't exist upstream..

Konrad