Re: [PATCH v8 16/25] gpu: nova-core: mm: Add page table walker for MMU v2/v3

[Gary Guo]

On Wed Feb 25, 2026 at 2:26 PM GMT, Joel Fernandes wrote:
> On 2026-02-25, Gary Guo <gary@xxxxxxxxxxx> wrote:
>> On 2026-02-24 22:53, Joel Fernandes wrote:
>>> +//! ## MMU v2 (Turing/Ampere/Ada) - 5 levels
>>> [...]
>>> +//! ## MMU v3 (Hopper+) - 6 levels
>>
>> I think this is called "4 levels" and "5 levels" in kernel MM rather than
>> "5 levels" and "6 levels".
>
> Actually, I think "5 levels" and "6 levels" is correct even by x86 kernel MM
> convention. In x86 "4-level paging", the 4 levels are PGD, PUD, PMD, PTE -
> the root page directory (PGD) IS counted as one of the 4 levels. Similarly,
> for the GPU MMU, counting the root PDB (L0) as a level gives us 5 levels for
> v2 (PDB/L0 through L4/PTE) and 6 levels for v3 (PDB/L0 through L5/PTE).
>
> This is also consistent with NVIDIA's own hardware definitions in the OpenRM
> headers (dev_mmu.h for Turing and Hopper) which define the page table entries
> for each of these levels. The virtual address bitfield spans L0 (bits 56:48)
> through L4 (bits 20:12) for v2, giving 5 distinct page table levels.
>
> FWIW, the existing nouveau driver also uses this convention - NVKM_VMM_LEVELS_MAX
> is defined as 6 in nvkm/subdev/mmu/vmm.c, and the GH100 page table descriptors
> in vmmgh100.c list all 6 levels.

So PDB is not just a single address, but a list of page table entries? If that's
the case, then the number of levels is indeed correct, but reading the code
gives me an impression otherwise.

Best,
Gary