[PATCH 0/5] DSI byte clock setting fixup

[Konrad Dybcio]

There's a conflict between the byte and byte_intf_div2 clocks trying to
set_rate on their common parent. The latter should follow the rate of
the former in one way or another anyway, so the fix here is to prevent
the latter from ratesetting the upstream PLL.

This series does just that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
---
Konrad Dybcio (5):
      clk: qcom: dispcc-glymur: Fix DSI byte clock rate setting
      clk: qcom: dispcc-kaanapali: Fix DSI byte clock rate setting
      clk: qcom: dispcc-milos: Fix DSI byte clock rate setting
      clk: qcom: dispcc-sm4450: Fix DSI byte clock rate setting
      clk: qcom: dispcc[01]-sa8775p: Fix DSI byte clock rate setting

 drivers/clk/qcom/dispcc-glymur.c    | 2 --
 drivers/clk/qcom/dispcc-kaanapali.c | 2 --
 drivers/clk/qcom/dispcc-milos.c     | 1 -
 drivers/clk/qcom/dispcc-sm4450.c    | 1 -
 drivers/clk/qcom/dispcc0-sa8775p.c  | 2 --
 drivers/clk/qcom/dispcc1-sa8775p.c  | 2 --
 6 files changed, 10 deletions(-)
---
base-commit: 3fa5e5702a82d259897bd7e209469bc06368bf31
change-id: 20260303-topic-dsi_byte_fixup-a6b4735e8d6e

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>