Re: [PATCH 1/5] PCI: Add CXL DVSEC control, lock, and range register definitions

[Srirangan Madhavan]

> These RWL defines really seem to be more kernel policy than spec
> definitions.  Do they really belong in the uAPI header?  Thanks,

Ack. I can move the RWL defines locally to where they are used.

________________________________________
From: Alex Williamson <alwilliamson@xxxxxxxxxx>
Sent: Friday, March 6, 2026 9:45 AM
To: Srirangan Madhavan
Cc: bhelgaas@xxxxxxxxxx; dan.j.williams@xxxxxxxxx; dave.jiang@xxxxxxxxx; jonathan.cameron@xxxxxxxxxx; ira.weiny@xxxxxxxxx; vishal.l.verma@xxxxxxxxx; alison.schofield@xxxxxxxxx; dave@xxxxxxxxxxxx; Jeshua Smith; Vikram Sethi; Sai Yashwanth Reddy Kancherla; Vishal Aslot; Shanker Donthineni; Manish Honap; Vidya Sagar; Jiandi An; Matt Ochs; Derek Schumacher; linux-cxl@xxxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
Subject: Re: [PATCH 1/5] PCI: Add CXL DVSEC control, lock, and range register definitions

On Fri, 6 Mar 2026 08:00:15 +0000
<smadhavan@xxxxxxxxxx> wrote:

> From: Srirangan Madhavan <smadhavan@xxxxxxxxxx>
>
> PCI: Add CXL DVSEC control, lock, and range register definitions
>
> Add register offset and field definitions for CXL DVSEC registers needed
> by CXL state save/restore across resets:
>
>   - CTRL2 (offset 0x10) and LOCK (offset 0x14) registers
>   - CONFIG_LOCK bit in the LOCK register
>   - RWL (read-write-when-locked) field masks for CTRL and range base
>     registers.
>
> Signed-off-by: Srirangan Madhavan <smadhavan@xxxxxxxxxx>
> ---
>  include/uapi/linux/pci_regs.h | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index ec1c54b5a310..6fdc20d7f5e6 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -1353,14 +1353,20 @@
>  #define   PCI_DVSEC_CXL_HDM_COUNT                    __GENMASK(5, 4)
>  #define  PCI_DVSEC_CXL_CTRL                          0xC
>  #define   PCI_DVSEC_CXL_MEM_ENABLE                   _BITUL(2)
> +#define   PCI_DVSEC_CXL_CTRL_RWL                     0x5FED
> +#define  PCI_DVSEC_CXL_CTRL2                         0x10
> +#define  PCI_DVSEC_CXL_LOCK                          0x14
> +#define   PCI_DVSEC_CXL_LOCK_CONFIG                  _BITUL(0)
>  #define  PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i)            (0x18 + (i * 0x10))
>  #define  PCI_DVSEC_CXL_RANGE_SIZE_LOW(i)             (0x1C + (i * 0x10))
>  #define   PCI_DVSEC_CXL_MEM_INFO_VALID                       _BITUL(0)
>  #define   PCI_DVSEC_CXL_MEM_ACTIVE                   _BITUL(1)
>  #define   PCI_DVSEC_CXL_MEM_SIZE_LOW                 __GENMASK(31, 28)
>  #define  PCI_DVSEC_CXL_RANGE_BASE_HIGH(i)            (0x20 + (i * 0x10))
> +#define   PCI_DVSEC_CXL_RANGE_BASE_HI_RWL            0xFFFFFFFF
>  #define  PCI_DVSEC_CXL_RANGE_BASE_LOW(i)             (0x24 + (i * 0x10))
>  #define   PCI_DVSEC_CXL_MEM_BASE_LOW                 __GENMASK(31, 28)
> +#define   PCI_DVSEC_CXL_RANGE_BASE_LO_RWL            0xF0000000
>
>  #define CXL_DVSEC_RANGE_MAX                          2
>

These RWL defines really seem to be more kernel policy than spec
definitions.  Do they really belong in the uAPI header?  Thanks,

Alex