[PATCH v2 01/11] dt-bindings: crypto: qcom,ice: Allow power-domain and iface clk

[Harshal Dev]

Update the inline-crypto engine DT binding to allow specifying up to two
clocks along with their names and associated power-domain. When the
'clk_ignore_unused' flag is not passed on the kernel command line
occasional unclocked ICE hardware register access are observed during ICE
driver probe based on the relative timing between the probe and the kernel
disabling the unused clocks. On the other hand, when the 'pd_ignore_unused'
flag is not passed on the command line, clock 'stuck' issues are
observed if the power-domain required by ICE hardware is unused and thus
disabled before ICE probe. To avoid these scenarios, the 'iface' clock and
the associated power-domain should be specified in the ICE device tree node
and the 'iface' clock should be voted on by the ICE driver during probe.

Fixes: f6ff91a47ac57 ("dt-bindings: crypto: Add Qualcomm Inline Crypto Engine")
Signed-off-by: Harshal Dev <harshal.dev@xxxxxxxxxxxxxxxx>
---
 .../bindings/crypto/qcom,inline-crypto-engine.yaml       | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index c3408dcf5d20..d9a0a8adf645 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -28,6 +28,16 @@ properties:
     maxItems: 1
 
   clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: ice_core_clk
+      - const: iface_clk
+
+  power-domains:
     maxItems: 1
 
 required:
@@ -45,6 +55,10 @@ examples:
       compatible = "qcom,sm8550-inline-crypto-engine",
                    "qcom,inline-crypto-engine";
       reg = <0x01d88000 0x8000>;
-      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+               <&gcc GCC_UFS_PHY_AHB_CLK>;
+      clock-names = "ice_core_clk",
+                    "iface_clk";
+      power-domains = <&gcc UFS_PHY_GDSC>;
     };
 ...

-- 
2.34.1