RE: [PATCH 02/20] cxl: Expose cxl subsystem specific functions for vfio

[Manish Honap]

> -----Original Message-----
> From: Dave Jiang <dave.jiang@xxxxxxxxx>
> Sent: 12 March 2026 22:19
> To: Manish Honap <mhonap@xxxxxxxxxx>; Aniket Agashe <aniketa@xxxxxxxxxx>;
> Ankit Agrawal <ankita@xxxxxxxxxx>; Alex Williamson
> <alwilliamson@xxxxxxxxxx>; Vikram Sethi <vsethi@xxxxxxxxxx>; Jason
> Gunthorpe <jgg@xxxxxxxxxx>; Matt Ochs <mochs@xxxxxxxxxx>; Shameer Kolothum
> Thodi <skolothumtho@xxxxxxxxxx>; alejandro.lucero-palau@xxxxxxx;
> dave@xxxxxxxxxxxx; jonathan.cameron@xxxxxxxxxx;
> alison.schofield@xxxxxxxxx; vishal.l.verma@xxxxxxxxx; ira.weiny@xxxxxxxxx;
> dan.j.williams@xxxxxxxxx; jgg@xxxxxxxx; Yishai Hadas <yishaih@xxxxxxxxxx>;
> kevin.tian@xxxxxxxxx
> Cc: Neo Jia <cjia@xxxxxxxxxx>; Tarun Gupta (SW-GPU) <targupta@xxxxxxxxxx>;
> Zhi Wang <zhiw@xxxxxxxxxx>; Krishnakant Jaju <kjaju@xxxxxxxxxx>; linux-
> kernel@xxxxxxxxxxxxxxx; linux-cxl@xxxxxxxxxxxxxxx; kvm@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH 02/20] cxl: Expose cxl subsystem specific functions
> for vfio
> 
> External email: Use caution opening links or attachments
> 
> 
> On 3/11/26 1:34 PM, mhonap@xxxxxxxxxx wrote:
> > From: Manish Honap <mhonap@xxxxxxxxxx>
> >
> > Below functions from CXL subsystem will be required in vfio-cxl for
> > supporting the type-2 device passthrough:
> >     cxl_find_regblock - To find component registers
> >     cxl_probe_component_regs - Probe HDM/RAS capabilities
> >
> > Make these functions available via declaring them from include header
> > instead of subsystem-specific header.
> >
> > Signed-off-by: Manish Honap <mhonap@xxxxxxxxxx>
> > ---
> >  drivers/cxl/cxl.h | 4 ----
> >  include/cxl/cxl.h | 7 +++++++
> >  2 files changed, 7 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index
> > 2b1f7d687a0e..10ddab3949ee 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -198,8 +198,6 @@ static inline int ways_to_eiw(unsigned int ways, u8
> *eiw)
> >  #define   CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48)
> >  #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
> >
> > -void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> > -                           struct cxl_component_reg_map *map);
> >  void cxl_probe_device_regs(struct device *dev, void __iomem *base,
> >                          struct cxl_device_reg_map *map);  int
> > cxl_map_device_regs(const struct cxl_register_map *map, @@ -211,8
> > +209,6 @@ enum cxl_regloc_type;  int cxl_count_regblock(struct pci_dev
> > *pdev, enum cxl_regloc_type type);  int
> > cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type
> type,
> >                              struct cxl_register_map *map, unsigned
> > int index); -int cxl_find_regblock(struct pci_dev *pdev, enum
> cxl_regloc_type type,
> > -                   struct cxl_register_map *map);
> >  int cxl_setup_regs(struct cxl_register_map *map);  struct cxl_dport;
> > int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport
> > *dport); diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index
> > 8456177b523e..610711e861d4 100644
> > --- a/include/cxl/cxl.h
> > +++ b/include/cxl/cxl.h
> > @@ -287,4 +287,11 @@ struct cxl_region *cxl_create_region(struct
> > cxl_root_decoder *cxlrd,
> >
> >  int cxl_get_hdm_reg_info(struct cxl_dev_state *cxlds, u32 *count,
> >                        resource_size_t *offset, resource_size_t
> > *size);
> > +struct pci_dev;
> > +enum cxl_regloc_type;
> > +int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> > +                   struct cxl_register_map *map); void
> > +cxl_probe_component_regs(struct device *dev, void __iomem *base,
> > +                           struct cxl_component_reg_map *map);
> 
> I do wonder if this needs an ifdef of CONFIG_CXL_BUS given cxl_core can be
> made as a module or disabled.
> 

Okay, I will update this section for #ifdef protection.

> 
> > +
> >  #endif /* __CXL_CXL_H__ */