Re: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC

[Geert Uytterhoeven]

Hi Biju,

On Thu, 5 Mar 2026 at 16:18, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> > On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@xxxxxxxxx> wrote:
> > > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > >
> > > Document the device tree bindings for the Renesas RZ/G3L SoC Clock
> > > Pulse Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5
> > > clocks compared to 1 clock on other SoCs.
> > >
> > > Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock,
> > > module
> > > clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add
> > > Reset definitions referring to registers CPG_RST_* in Section 4.4.3
> > > ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
> > >
> > > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > > --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > @@ -28,19 +28,30 @@ properties:
> > >        - renesas,r9a07g044-cpg # RZ/G2{L,LC}
> > >        - renesas,r9a07g054-cpg # RZ/V2L
> > >        - renesas,r9a08g045-cpg # RZ/G3S
> > > +      - renesas,r9a08g046-cpg # RZ/G3L
> > >        - renesas,r9a09g011-cpg # RZ/V2M
> > >
> > >    reg:
> > >      maxItems: 1
> > >
> > >    clocks:
> > > -    maxItems: 1
> > > +    minItems: 1
> > > +    items:
> > > +      - description: Clock source to CPG can be either from external clock
> > > +                     input (EXCLK) or crystal oscillator (XIN/XOUT).
> > > +      - description: ETH0 TXC clock input
> > > +      - description: ETH0 RXC clock input
> > > +      - description: ETH1 TXC clock input
> > > +      - description: ETH1 RXC clock input
> > >
> > >    clock-names:
> > > -    description:
> > > -      Clock source to CPG can be either from external clock input (EXCLK) or
> > > -      crystal oscillator (XIN/XOUT).
> > > -    const: extal
> > > +    minItems: 1
> > > +    items:
> > > +      - const: extal
> > > +      - const: eth0_txc_tx_clk
> > > +      - const: eth0_rxc_rx_clk
> > > +      - const: eth1_txc_tx_clk
> > > +      - const: eth1_rxc_rx_clk
> >
> > Are you sure about these four clocks? On which pins are they input?
>
> From Figure 4.4-5 Block Diagram of the Deformed Clock System (4), page 789
>
> These clks are external source clks connected to CPG_ETH_SSEL mux for
> selecting rx/tx clks.
>
> In RGMII case, currently on RZ/G3L SMARC EVK:
>
> For Tx: we select DIV_ETH0_TR (SEL_ETH0A_SET)
> For Rx: we select ETH0_RXC_RX_CLK_IN (SEL_ETH0B_SET)

Sure, these clocks are indeed shown in that Figure, and referenced in
the CPG_ETH_SSEL register documentation, but where do they originate
from? On which pins are they supplied?

> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/r9a08g046-cpg.h
> > > @@ -0,0 +1,343 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > + *
> > > + * Copyright (C) 2026 Renesas Electronics Corp.
> > > + */
> > > +#ifndef __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> > > +#define __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> > > +
> > > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > > +
> > > +/* R9A08G046 CPG Core Clocks */
> >
> > [...]
> >
> > > +#define R9A08G046_OSCCLK               52
> > > +#define R9A08G046_OSCCLK2              53
> > > +#define R9A08G046_CLK_P4_DIV2          54
> >
> > CLK_P4_DIV2 looks like a purely internal clock to me.
>
> Page 3918 Figure 7.9-1 Block Diagram of CAN-FD
>
> Peripheral clk,
> RAM clk,
> CAN external clk
>
> Then, CANFD clk which is DIV2 clk of Peripheral clk, so thought of
> modelling this as Core clk. I may be wrong here??
>
> Maybe I will drop this now and revisit later when we add support for CANFD??

That may be the better option.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds