RE: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 13 March 2026 14:06
> Subject: Re: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC
> 
> Hi Biju,
> 
> On Thu, 5 Mar 2026 at 16:18, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> On Tue, 3 Feb 2026
> > > at 11:30, Biju <biju.das.au@xxxxxxxxx> wrote:
> > > > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > >
> > > > Document the device tree bindings for the Renesas RZ/G3L SoC Clock
> > > > Pulse Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has
> > > > 5 clocks compared to 1 clock on other SoCs.
> > > >
> > > > Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock,
> > > > module clock outputs, as listed in section 4.4.2 ("Clock List
> > > > r1.00") and add Reset definitions referring to registers CPG_RST_*
> > > > in Section 4.4.3
> > > > ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
> > > >
> > > > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > >
> > > > ---
> > > > a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.ya
> > > > +++ ml
> > > > @@ -28,19 +28,30 @@ properties:
> > > >        - renesas,r9a07g044-cpg # RZ/G2{L,LC}
> > > >        - renesas,r9a07g054-cpg # RZ/V2L
> > > >        - renesas,r9a08g045-cpg # RZ/G3S
> > > > +      - renesas,r9a08g046-cpg # RZ/G3L
> > > >        - renesas,r9a09g011-cpg # RZ/V2M
> > > >
> > > >    reg:
> > > >      maxItems: 1
> > > >
> > > >    clocks:
> > > > -    maxItems: 1
> > > > +    minItems: 1
> > > > +    items:
> > > > +      - description: Clock source to CPG can be either from external clock
> > > > +                     input (EXCLK) or crystal oscillator (XIN/XOUT).
> > > > +      - description: ETH0 TXC clock input
> > > > +      - description: ETH0 RXC clock input
> > > > +      - description: ETH1 TXC clock input
> > > > +      - description: ETH1 RXC clock input
> > > >
> > > >    clock-names:
> > > > -    description:
> > > > -      Clock source to CPG can be either from external clock input (EXCLK) or
> > > > -      crystal oscillator (XIN/XOUT).
> > > > -    const: extal
> > > > +    minItems: 1
> > > > +    items:
> > > > +      - const: extal
> > > > +      - const: eth0_txc_tx_clk
> > > > +      - const: eth0_rxc_rx_clk
> > > > +      - const: eth1_txc_tx_clk
> > > > +      - const: eth1_rxc_rx_clk
> > >
> > > Are you sure about these four clocks? On which pins are they input?
> >
> > From Figure 4.4-5 Block Diagram of the Deformed Clock System (4), page
> > 789
> >
> > These clks are external source clks connected to CPG_ETH_SSEL mux for
> > selecting rx/tx clks.
> >
> > In RGMII case, currently on RZ/G3L SMARC EVK:
> >
> > For Tx: we select DIV_ETH0_TR (SEL_ETH0A_SET) For Rx: we select
> > ETH0_RXC_RX_CLK_IN (SEL_ETH0B_SET)
> 
> Sure, these clocks are indeed shown in that Figure, and referenced in the CPG_ETH_SSEL register
> documentation, but where do they originate from? On which pins are they supplied?

Figure 6.3-1 Block Diagram of the Ethernet Interface 

and

1.3.3 Clock Pin Specifications
Table 1.3-3 List of Pin Functions (1/2)

For Rx this clock is supplied by PHY on the RZ/G3L SMARC SoM Module.
RZ_ETH0_RXC is the pin.
 
For Tx this clock is supplied by the SoC(RZ_ETH0_TXC)

Cheers,
Biju