Re: [PATCH v4 8/8] media: qcom: iris: split platform data from firmware data

[Dikshita Agarwal]

On 3/14/2026 12:53 AM, Dmitry Baryshkov wrote:
> On Fri, Mar 13, 2026 at 01:37:42PM +0530, Dikshita Agarwal wrote:
>>
>>
>> On 3/13/2026 9:00 AM, Dmitry Baryshkov wrote:
>>> Finalize the logical separation of the software and hardware interface
>>> descriptions by moving hardware properties to the files specific to the
>>> particular VPU version.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
>>> ---
>>>  drivers/media/platform/qcom/iris/Makefile          |   6 +-
>>>  .../iris/{iris_platform_gen1.c => iris_hfi_gen1.c} | 133 -------------
>>>  .../iris/{iris_platform_gen2.c => iris_hfi_gen2.c} | 218 ---------------------
>>>  .../platform/qcom/iris/iris_platform_common.h      |   4 +
>>>  .../platform/qcom/iris/iris_platform_sm8250.h      |  29 +++
>>>  .../platform/qcom/iris/iris_platform_sm8550.h      |  31 +++
>>>  .../media/platform/qcom/iris/iris_platform_vpu2.c  | 124 ++++++++++++
>>>  .../media/platform/qcom/iris/iris_platform_vpu3.c  | 210 ++++++++++++++++++++
>>>  8 files changed, 402 insertions(+), 353 deletions(-)
>>>
>>
>>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
>>> new file mode 100644
>>> index 000000000000..74c8f38e849b
>>> --- /dev/null
>>> +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
>>> @@ -0,0 +1,124 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
>>> + */
>>> +
>>> +#include "iris_core.h"
>>> +#include "iris_ctrls.h"
>>> +#include "iris_platform_common.h"
>>> +#include "iris_resources.h"
>>> +#include "iris_hfi_gen1.h"
>>> +#include "iris_hfi_gen1_defines.h"
>>> +#include "iris_vpu_buffer.h"
>>> +#include "iris_vpu_common.h"
>>> +#include "iris_instance.h"
>>> +
>>> +#include "iris_platform_sc7280.h"
>>> +#include "iris_platform_sm8250.h"
>>> +
>>> +static struct iris_fmt platform_fmts_sm8250_dec[] = {
>>
>> How about naming this as platform_fmts_vpu2_dec ?
> 
> Ack
> 
>>
>>> +	[IRIS_FMT_H264] = {
>>> +		.pixfmt = V4L2_PIX_FMT_H264,
>>> +		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
>>> +	},
>>> +	[IRIS_FMT_HEVC] = {
>>> +		.pixfmt = V4L2_PIX_FMT_HEVC,
>>> +		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
>>> +	},
>>> +	[IRIS_FMT_VP9] = {
>>> +		.pixfmt = V4L2_PIX_FMT_VP9,
>>> +		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
>>> +	},
>>> +};
>>> +
>>> +static struct platform_inst_caps platform_inst_cap_sm8250 = {
>>
>> platform_inst_cap_vpu2 ?
> 
> I thought that these params might change from platform to platform.
> IIRC, SM8350 supported smaller frames in some cases.

That's right, and in that case the structure can be defined in the SOC
header file.

Thanks,
Dikshita
> 
>>
>>> +	.min_frame_width = 128,
>>> +	.max_frame_width = 8192,
>>> +	.min_frame_height = 128,
>>> +	.max_frame_height = 8192,
>>> +	.max_mbpf = 138240,
>>> +	.mb_cycles_vsp = 25,
>>> +	.mb_cycles_vpp = 200,
>>> +	.max_frame_rate = MAXIMUM_FPS,
>>> +	.max_operating_rate = MAXIMUM_FPS,
>>> +};
>>> +
>>> +static const struct icc_info sm8250_icc_table[] = {
>>
>> icc_table_vpu2 ?
> 
> Aren't the limits generally platform-dependent?
> 
>>
>>> +	{ "cpu-cfg",    1000, 1000     },
>>> +	{ "video-mem",  1000, 15000000 },
>>> +};
>>> +
>>> +static const char * const sm8250_clk_reset_table[] = { "bus", "core" };
>>
>> clk_reset_table_vpu2 ? and so on.
> 
> Ack.
> 
>>
>>> +
>>> +static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" };
>>> +
>>> +static const struct tz_cp_config tz_cp_config_sm8250[] = {
>>> +	{
>>> +		.cp_start = 0,
>>> +		.cp_size = 0x25800000,
>>> +		.cp_nonpixel_start = 0x01000000,
>>> +		.cp_nonpixel_size = 0x24800000,
>>> +	},
>>> +};
>>> +
>>> +const struct iris_platform_data sc7280_data = {
>>> +	.firmware_data = &iris_hfi_gen1_data,
>>> +	.vpu_ops = &iris_vpu2_ops,
>>> +	.icc_tbl = sm8250_icc_table,
>>> +	.icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),
>>> +	.bw_tbl_dec = sc7280_bw_table_dec,
>>> +	.bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec),
>>> +	.pmdomain_tbl = sm8250_pmdomain_table,
>>> +	.pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
>>> +	.opp_pd_tbl = sc7280_opp_pd_table,
>>> +	.opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
>>> +	.clk_tbl = sc7280_clk_table,
>>> +	.clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),
>>> +	.opp_clk_tbl = sc7280_opp_clk_table,
>>> +	/* Upper bound of DMA address range */
>>> +	.dma_mask = 0xe0000000 - 1,
>>> +	.fwname = "qcom/vpu/vpu20_p1.mbn",
>>> +	.inst_iris_fmts = platform_fmts_sm8250_dec,
>>> +	.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec),
>>> +	.inst_caps = &platform_inst_cap_sm8250,
>>> +	.tz_cp_config_data = tz_cp_config_sm8250,
>>> +	.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
>>> +	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
>>> +	.num_vpp_pipe = 1,
>>> +	.no_aon = true,
>>> +	.max_session_count = 16,
>>> +	.max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
>>> +	/* max spec for SC7280 is 4096x2176@60fps */
>>> +	.max_core_mbps = 4096 * 2176 / 256 * 60,
>>> +};
>>> +
>>> +const struct iris_platform_data sm8250_data = {
>>> +	.firmware_data = &iris_hfi_gen1_data,
>>> +	.vpu_ops = &iris_vpu2_ops,
>>> +	.icc_tbl = sm8250_icc_table,
>>> +	.icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),
>>> +	.clk_rst_tbl = sm8250_clk_reset_table,
>>> +	.clk_rst_tbl_size = ARRAY_SIZE(sm8250_clk_reset_table),
>>> +	.bw_tbl_dec = sm8250_bw_table_dec,
>>> +	.bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec),
>>> +	.pmdomain_tbl = sm8250_pmdomain_table,
>>> +	.pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
>>> +	.opp_pd_tbl = sm8250_opp_pd_table,
>>> +	.opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
>>> +	.clk_tbl = sm8250_clk_table,
>>> +	.clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
>>> +	.opp_clk_tbl = sm8250_opp_clk_table,
>>> +	/* Upper bound of DMA address range */
>>> +	.dma_mask = 0xe0000000 - 1,
>>> +	.fwname = "qcom/vpu-1.0/venus.mbn",
>>> +	.inst_iris_fmts = platform_fmts_sm8250_dec,
>>> +	.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec),
>>> +	.inst_caps = &platform_inst_cap_sm8250,
>>> +	.tz_cp_config_data = tz_cp_config_sm8250,
>>> +	.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
>>> +	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
>>> +	.num_vpp_pipe = 4,
>>> +	.max_session_count = 16,
>>> +	.max_core_mbpf = NUM_MBS_8K,
>>> +	.max_core_mbps = ((7680 * 4320) / 256) * 60,
>>> +};
>>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3.c
>>> new file mode 100644
>>> index 000000000000..2c0e5be72920
>>> --- /dev/null
>>> +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3.c
>>
>> iris_platform_vpu3x.c ?
>>
>>> @@ -0,0 +1,210 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
>>> + * Copyright (c) 2025 Linaro Ltd
>>> + */
>>> +
>>> +#include "iris_core.h"
>>> +#include "iris_ctrls.h"
>>> +#include "iris_hfi_gen2.h"
>>> +#include "iris_hfi_gen2_defines.h"
>>> +#include "iris_platform_common.h"
>>> +#include "iris_vpu_buffer.h"
>>> +#include "iris_vpu_common.h"
>>> +
>>> +#include "iris_platform_qcs8300.h"
>>> +#include "iris_platform_sm8550.h"
>>> +#include "iris_platform_sm8650.h"
>>> +#include "iris_platform_sm8750.h"
>>> +
>>> +#define VIDEO_ARCH_LX 1
>>> +
>>> +static struct iris_fmt platform_fmts_sm8550_dec[] = {
>>
>> platform_fmts_vpu3x_dec ?
> 
> Ack
> 
>>
>>> +	[IRIS_FMT_H264] = {
>>> +		.pixfmt = V4L2_PIX_FMT_H264,
>>> +		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
>>> +	},
>>> +	[IRIS_FMT_HEVC] = {
>>> +		.pixfmt = V4L2_PIX_FMT_HEVC,
>>> +		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
>>> +	},
>>> +	[IRIS_FMT_VP9] = {
>>> +		.pixfmt = V4L2_PIX_FMT_VP9,
>>> +		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
>>> +	},
>>> +	[IRIS_FMT_AV1] = {
>>> +		.pixfmt = V4L2_PIX_FMT_AV1,
>>> +		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
>>> +	},
>>> +};
>>> +
>>> +static const struct icc_info sm8550_icc_table[] = {
>>
>> icc_table_vpu3x ? and so on.
>>
>> Thanks,
>> Dikshita
>>
>>> +	{ "cpu-cfg",    1000, 1000     },
>>> +	{ "video-mem",  1000, 15000000 },
>>> +};
>>> +
>>> +static const struct bw_info sm8550_bw_table_dec[] = {
>>> +	{ ((4096 * 2160) / 256) * 60, 1608000 },
>>> +	{ ((4096 * 2160) / 256) * 30,  826000 },
>>> +	{ ((1920 * 1080) / 256) * 60,  567000 },
>>> +	{ ((1920 * 1080) / 256) * 30,  294000 },
>>> +};
>>> +
>>> +static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" };
>>> +
>>> +static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" };
>>> +
>>> +static const char * const sm8550_opp_clk_table[] = {
>>> +	"vcodec0_core",
>>> +	NULL,
>>> +};
>>> +
>>> +static const struct tz_cp_config tz_cp_config_sm8550[] = {
>>> +	{
>>> +		.cp_start = 0,
>>> +		.cp_size = 0x25800000,
>>> +		.cp_nonpixel_start = 0x01000000,
>>> +		.cp_nonpixel_size = 0x24800000,
>>> +	},
>>> +};
>>
>