Re: [PATCH] clk: qcom: rcg2: expand frac table for mdss_pixel_clk_src

[Bjorn Andersson]

On Sat, 21 Mar 2026 17:50:28 +0800, Pengyu Luo wrote:
> Recently, when testing 10-bit dsi C-PHY panel, clks are different
> from the usual. (dsi0_phy_pll_out_dsiclk's parent is dsi0_pll_bit_clk
> now (dsiclk_sel = 0)) And we failed to set dsiclk's children.
> 
> dsi_link_clk_set_rate_6g: Set clk rates: pclk=172992000, byteclk=108120000
> 
> byteclk was set first to 108120000, so the vco rate was set to
> 108120000 * 7 * 1 * 1 = 756840000. When we was trying to set
> 172992000 on mdss_pixel_clk_src later.
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: rcg2: expand frac table for mdss_pixel_clk_src
      commit: 0f5c8f03d990f9be9908a08a701c324e113554d2

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>