Re: [PATCH v6 4/4] iio: adc: ad4691: add SPI offload support

[David Lechner]

On 4/6/26 8:30 AM, Sabau, Radu bogdan wrote:
> 
> 
>> -----Original Message-----
>> From: Sabau, Radu bogdan
>> Sent: Monday, April 6, 2026 2:08 PM
>>
>> ...
>>
>>>>>  #define AD4691_CHANNEL(ch)
>>>> 	\
>>>>>  	{								\
>>>>>  		.type = IIO_VOLTAGE,					\
>>>>> @@ -122,11 +155,9 @@ struct ad4691_chip_info {
>>>>>  		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE),
>>>> 	\
>>>>>  		.channel = ch,						\
>>>>>  		.scan_index = ch,					\
>>>>> -		.scan_type = {						\
>>>>> -			.sign = 'u',					\
>>>>> -			.realbits = 16,					\
>>>>> -			.storagebits = 16,				\
>>>>> -		},							\
>>>>> +		.has_ext_scan_type = 1,
>>>> 	\
>>>>> +		.ext_scan_type = ad4691_scan_types,			\
>>>>> +		.num_ext_scan_type = ARRAY_SIZE(ad4691_scan_types),
>>>> 	\
>>>>
>>>> Usually, we just make two separte ad4691_chip_info structs for offload
>>>> vs. not offload.
>>>>
>>>> ext_scan_type is generally only used when the scan type can change
>>>> dynamically after probe.
>>>>
>>>
>>> So, just to be clear, you are saying I should have different chip_info structs
>>> and change the triggered-buffer for offload ones if offload is present?
>>> I am asking since offload has different scan types as well, and this would
>>> mean 3 different chip_info structs for each chip -> total of 12 chip_info
>> structs,
>>> each with a different channel array, or perhaps there is a more compact way
>>> to have this implemented.
>>> I could make the channel arrays use the same macro and have the scan_type
>>> reversed to storage and shift done as parameters.
>>>
>>
>> I have given this a thought and I think this could be done in a more compact
>> way:
>>
>> 1. Parametrize AD4691_CHANNEL to accept storagebits and shift, then define
>> 4 channel
>> arrays:
>>
>> 	- ad4691_channels[] - 16ch + timestamp (triggered-buffer path)
>> 	- ad4693_channels[] - 8ch + timestamp (triggered-buffer path)
>> 	- ad4691_offload_cnv_channels[] - 16 entries, storagebits=32, shift =
>> 0
>> 	- ad4691_offload_manual_channels[] - 16 entries, storagebits=32,
>> shift=16
>>
>>     The two offload arrays are shared across both chip families. Since
>> num_channels
>>     bound the interation in the IIO core, the 8ch chips simply use the first 8
>> entries of
>>     the 16-entry offload arrays. Triggered-buffer path would need different
>> channel
>>     arrays since the timestamp index would be different, and offload doesn't use
>>     timestamp.
>>
>> 2. chip_info could then stay at 2 structs, and have channels selected at probe
>> for the
>> indio_dev, or have 4 chip info structs each having its own channels assigned,
>> and only
>> num_channels could be changed at probe.
>>
> 
> I also have to mention that the oversampling commit would then implement
> AD4691_MANUAL_CHANNEL macro which would miss the OVERSAMPLING
> infomask, and offload_manual_channels will be declared using it.
> More than this, that commit would also add other ad4691_manual_channels[]
> and ad4693_manual_channels[] arrays that would use that MACRO as well.
> 
> Then, chip_info would have ad4691/93_channels assigned to it by default,
> and indio_dev->channels will later be assigned at probe, depending on the
> mode and offload.
> 
> If different chip_info structs would be wanted still, then my best guess is
> to have different info structures (perhaps new types) in chip_info by default.
> Something like *sw_info and *offload_info.

Yes, this is how I would do it too.

> Each one would contain all the pre-defined channel arrays in them
> (channels and manual_channels) and so have ad4691_sw_info and ad4691_offload_info.
> After so, chip_info will also contain besides these 2 info structures, num_channels and max_rate.
> At probe indio_dev assignments will be made from the chip_info entirely.
> 
> What's your guys take on this? I am keen to hearing your thoughts about this.
> 
> Thanks,
> Radu
>