Re: [PATCH v2 4/8] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up
From: Manivannan Sadhasivam
Date: Wed May 06 2026 - 12:10:50 EST
On Wed, May 06, 2026 at 11:23:42PM +0800, Hans Zhang wrote:
> Set cdns_pcie.max_link_speed to the maximum supported link speed
> (obtained from the device tree property "max-link-speed") in
> j721e_pcie_set_link_speed(). This activates the post-link delay logic
> added in cdns_pcie_host_start_link() when the controller supports
> speeds greater than 5 GT/s.
>
> As required by PCIe r6.0 sec 6.6.1, and following the same approach as
> commit 80dc18a0cba8d ("PCI: dwc: Ensure that dw_pcie_wait_for_link()
> waits 100 ms after link up"), this ensures a 100 ms delay after link
> training completes before any Configuration Request is sent.
>
> Signed-off-by: Hans Zhang <18255117159@xxxxxxx>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index bfdfe98d5aba..ee85b8e04f5b 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -206,6 +206,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
> (pcie_get_link_speed(link_speed) == PCI_SPEED_UNKNOWN))
> link_speed = 2;
>
> + pcie->cdns_pcie.max_link_speed = link_speed;
What about other glue drivers?
- Mani
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