Re: [PATCH v2 4/8] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up

From: Hans Zhang

Date: Wed May 06 2026 - 12:13:57 EST




On 5/7/26 00:04, Manivannan Sadhasivam wrote:
On Wed, May 06, 2026 at 11:23:42PM +0800, Hans Zhang wrote:
Set cdns_pcie.max_link_speed to the maximum supported link speed
(obtained from the device tree property "max-link-speed") in
j721e_pcie_set_link_speed(). This activates the post-link delay logic
added in cdns_pcie_host_start_link() when the controller supports
speeds greater than 5 GT/s.

As required by PCIe r6.0 sec 6.6.1, and following the same approach as
commit 80dc18a0cba8d ("PCI: dwc: Ensure that dw_pcie_wait_for_link()
waits 100 ms after link up"), this ensures a 100 ms delay after link
training completes before any Configuration Request is sent.

Signed-off-by: Hans Zhang <18255117159@xxxxxxx>
---
drivers/pci/controller/cadence/pci-j721e.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index bfdfe98d5aba..ee85b8e04f5b 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -206,6 +206,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
(pcie_get_link_speed(link_speed) == PCI_SPEED_UNKNOWN))
link_speed = 2;
+ pcie->cdns_pcie.max_link_speed = link_speed;

What about other glue drivers?

Hi Mani,

pci-sky1.c:
There is no time to handle the corresponding DTS yet, and the attribute "max-link-speed" has not been parsed either. There will be a plan for the subsequent upstream.

pcie-sg2042.c:
I'm not familiar with this product.


Do you mean something like a dwc driver, similar to being placed in the file drivers/pci/controller/dwc/pcie-designware.c?
pci->max_link_speed = of_pci_get_max_link_speed(np);

For the Cadence driver, it is located in drivers/pci/controller/cadence/pcie-cadence-host-common.c.


Best regards,
Hans


- Mani