Re: [PATCH v2 1/2] dt-bindings: cpufreq: qcom-hw: Document Shikra CPUFREQ Hardware

[Imran Shaik]

On 20-05-2026 03:50 pm, Krzysztof Kozlowski wrote:
> On Tue, May 19, 2026 at 10:58:03PM +0530, Imran Shaik wrote:
> > The Qualcomm Shikra cpufreq hardware is functionally identical to EPSS,
> > but supports only up to 12 frequency lookup table (LUT) entries. Introduce
> > Shikra specific bindings to represent this constrained EPSS variant.
> >
> > Signed-off-by: Imran Shaik <imran.shaik@xxxxxxxxxxxxxxxx>
> > ---
> >   .../bindings/cpufreq/shikra-cpufreq-qcom-hw.yaml   | 133 +++++++++++++++++++++
>
> Filename must match compatible. Please read writing-bindings doc.

Sure, kept it aligned with the existing epss file name. Will rename it 
to match the Shikra compatible name.

> >   1 file changed, 133 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/cpufreq/shikra-cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/shikra-cpufreq-qcom-hw.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..52079ed661671554fcca8677409ee11199f5727b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/cpufreq/shikra-cpufreq-qcom-hw.yaml
> > @@ -0,0 +1,133 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/cpufreq/shikra-cpufreq-qcom-hw.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: CPUFREQ HW for Qualcomm Shikra SoC
> > +
> > +maintainers:
> > +  - Imran Shaik <imran.shaik@xxxxxxxxxxxxxxxx>
> > +  - Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
> > +
> > +description: |
> > +
>
> Drop blank line

Sure.

> > +  CPUFREQ HW is a hardware engine used by some Qualcomm SoCs to manage
> > +  frequency in hardware. It is capable of controlling frequency for
> > +  multiple clusters.
> > +
> > +  The Qualcomm Shikra CPUFREQ HW supports up to 12 frequency lookup table
> > +  (LUT) entries.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - qcom,shikra-cpufreq-epss
>
> cpufreq is Linux term. How the device called in manual? EPSS? cpufreq?
> cpufreq-epss?

Its EPSS. Will update the compatible name as qcom,shikra-epss.

> > +
> > +  reg:
> > +    items:
> > +      - description: Frequency domain 0 register region
> > +      - description: Frequency domain 1 register region
> > +
> > +  reg-names:
> > +    items:
> > +      - const: freq-domain0
> > +      - const: freq-domain1
> > +
> > +  clocks:
> > +    items:
> > +      - description: XO Clock
> > +      - description: GPLL0 Clock
> > +
> > +  clock-names:
> > +    items:
> > +      - const: xo
> > +      - const: alternate
> > +
> > +  interrupts:
> > +    items:
> > +      - description: IRQ line for DCVSH 0
> > +      - description: IRQ line for DCVSH 1
> > +
> > +  interrupt-names:
> > +    items:
> > +      - const: dcvsh-irq-0
> > +      - const: dcvsh-irq-1
> > +
> > +  '#freq-domain-cells':
> > +    const: 1
> > +
> > +  '#clock-cells':
> > +    const: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - '#freq-domain-cells'
>
> Why interrupts are not required?
>
> Why clock-cells are missing? The device is a clock provider, no? Does it
> differ per each board?

I will add clock-cells also to required list.

> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/qcom,rpmcc.h>
> > +
> > +      cpus {
> > +        #address-cells = <2>;
> > +        #size-cells = <0>;
> > +
> > +        cpu0: cpu@0 {
> > +          device_type = "cpu";
> > +          compatible = "arm,cortex-a55";
> > +          reg = <0x0 0x0>;
> > +          enable-method = "psci";
> > +          qcom,freq-domain = <&cpufreq_hw 0>;
> > +          clocks = <&cpufreq_hw 0>;
> > +        };
> > +
> > +        cpu1: cpu@100 {
> > +          device_type = "cpu";
> > +          compatible = "arm,cortex-a55";
> > +          reg = <0x0 0x100>;
> > +          enable-method = "psci";
> > +          qcom,freq-domain = <&cpufreq_hw 0>;
> > +          clocks = <&cpufreq_hw 0>;
> > +        };
> > +
> > +        cpu2: cpu@200 {
> > +          device_type = "cpu";
> > +          compatible = "arm,cortex-a55";
> > +          reg = <0x0 0x200>;
> > +          enable-method = "psci";
> > +          qcom,freq-domain = <&cpufreq_hw 0>;
> > +          clocks = <&cpufreq_hw 0>;
> > +        };
> > +
> > +        cpu3: cpu@300 {
> > +          device_type = "cpu";
> > +          compatible = "arm,cortex-a78c";
> > +          reg = <0x0 0x300>;
> > +          enable-method = "psci";
> > +          qcom,freq-domain = <&cpufreq_hw 1>;
> > +          clocks = <&cpufreq_hw 1>;
> > +        };
> > +      };
>
> Drop all nodes above.

Sure, will drop in next series.

> > +
> > +    soc {
> > +      #address-cells = <1>;
> > +      #size-cells = <1>;
> > +
> > +      cpufreq@fd91000 {
> > +        compatible = "qcom,shikra-cpufreq-epss";
> > +        reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>;
> > +        reg-names = "freq-domain0", "freq-domain1";
> > +
> > +        clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gpll0>;
> > +        clock-names = "xo", "alternate";
>
> Incomplete example.

Sure, will update with IRQ details as well in next series.

Thanks,
Imran

> > +
> > +        #freq-domain-cells = <1>;
> > +        #clock-cells = <1>;
> > +      };
> > +    };
> > +...
> >
> > --
> > 2.34.1