Re: [PATCH 2/3] media: i2c: add imx576 image sensor driver

From: Himanshu Bhavani

Date: Thu May 21 2026 - 01:44:42 EST

Hi Laurent,

>On Wed, May 20, 2026 at 05:26:34PM +0530, Himanshu Bhavani wrote:
>> Add a v4l2 subdevice driver for the Sony imx576 sensor.
>>
>> The Sony IMX576 image sensor with an active
>> array size of 5760 x 4312
>>
>> The following features are supported:
>> - Manual exposure an gain control support
>> - vblank/hblank control support
>> - Supported resolution: 2880 x 2156 30fps (SRGGB10)
>>
>> Signed-off-by: Himanshu Bhavani <himanshu.bhavani@xxxxxxxxxxxxxxxxx>
>> ---
>> MAINTAINERS | 1 +
>> drivers/media/i2c/Kconfig | 10 +
>> drivers/media/i2c/Makefile | 1 +
>> drivers/media/i2c/imx576.c | 1029 ++++++++++++++++++++++++++++++++++++
>> 4 files changed, 1041 insertions(+)
>> create mode 100644 drivers/media/i2c/imx576.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 1b15fa355e8b..768a1eb3627a 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -24862,6 +24862,7 @@ M: Hardevsinh Palaniya <hardevsinh.palaniya@xxxxxxxxxxxxxxxxx>
>> L: linux-media@xxxxxxxxxxxxxxx
>> S: Maintained
>> F: Documentation/devicetree/bindings/media/i2c/sony,imx576.yaml
>> +F: drivers/media/i2c/imx576.c
>>
>> SONY MEMORYSTICK SUBSYSTEM
>> M: Maxim Levitsky <maximlevitsky@xxxxxxxxx>
>> diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
>> index fc2954098eaf..05d1e69c2f33 100644
>> --- a/drivers/media/i2c/Kconfig
>> +++ b/drivers/media/i2c/Kconfig
>> @@ -288,6 +288,16 @@ config VIDEO_IMX415
>> To compile this driver as a module, choose M here: the
>> module will be called imx415.
>>
>> +config VIDEO_IMX576
>> + tristate "Sony IMX576 sensor support"
>> + select V4L2_CCI_I2C
>> + help
>> + This is a Video4Linux2 sensor driver for the Sony
>> + IMX576 camera.
>> +
>> + To compile this driver as a module, choose M here: the
>> + module will be called imx576.
>> +
>> config VIDEO_MAX9271_LIB
>> tristate
>>
>> diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
>> index 90b276a7417a..e96c083e03d9 100644
>> --- a/drivers/media/i2c/Makefile
>> +++ b/drivers/media/i2c/Makefile
>> @@ -61,6 +61,7 @@ obj-$(CONFIG_VIDEO_IMX335) += imx335.o
>> obj-$(CONFIG_VIDEO_IMX355) += imx355.o
>> obj-$(CONFIG_VIDEO_IMX412) += imx412.o
>> obj-$(CONFIG_VIDEO_IMX415) += imx415.o
>> +obj-$(CONFIG_VIDEO_IMX576) += imx576.o
>> obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
>> obj-$(CONFIG_VIDEO_ISL7998X) += isl7998x.o
>> obj-$(CONFIG_VIDEO_KS0127) += ks0127.o
>> diff --git a/drivers/media/i2c/imx576.c b/drivers/media/i2c/imx576.c
>> new file mode 100644
>> index 000000000000..910cbcfb6031
>> --- /dev/null
>> +++ b/drivers/media/i2c/imx576.c
>> @@ -0,0 +1,1029 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * V4L2 Support for the IMX576
>> + *
>> + * Copyright (C) 2026 Silicon Signals Pvt. Ltd.
>> + *
>> + * Copyright (C) 2024 Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
>> + */
>> +
>> +#include <linux/array_size.h>
>> +#include <linux/bitops.h>
>> +#include <linux/clk.h>
>> +#incluLaurentde <linux/container_of.h>
>> +#include <linux/delay.h>
>> +#include <linux/device/devres.h>
>> +#include <linux/err.h>
>> +#include <linux/gpio/consumer.h>
>> +#include <linux/i2c.h>
>> +#include <linux/module.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/regulator/consumer.h>
>> +#include <linux/types.h>
>> +#include <linux/time.h>
>> +#include <linux/units.h>
>> +
>> +#include <media/v4l2-cci.h>
>> +#include <media/v4l2-ctrls.h>
>> +#include <media/v4l2-device.h>
>> +#include <media/v4l2-fwnode.h>
>> +#include <media/v4l2-mediabus.h>
>> +
>> +#define IMX576_INCLK_RATE (24 * HZ_PER_MHZ)
>> +
>> +#define IMX576_REG_CHIP_ID CCI_REG16(0x0016)
>> +#define IMX576_CHIP_ID 0x0576
>> +
>> +#define IMX576_REG_MODE_SELECT CCI_REG8(0x0100)
>> +#define IMX576_MODE_STANDBY 0x00
>> +#define IMX576_MODE_STREAMING 0x01
>> +
>> +#define IMX576_REG_HOLD CCI_REG8(0x0104)
>> +
>> +#define IMX576_REG_EXPOSURE CCI_REG16(0x0202)
>> +#define IMX576_EXPOSURE_MIN 8
>> +#define IMX576_EXPOSURE_OFFSET 22
>> +#define IMX576_EXPOSURE_STEP 1
>> +#define IMX576_EXPOSURE_DEFAULT 0x0648
>> +
>> +#define IMX576_REG_ANALOG_GAIN CCI_REG16(0x0204)
>> +#define IMX576_ANA_GAIN_MIN 0
>> +#define IMX576_ANA_GAIN_MAX 978
>> +#define IMX576_ANA_GAIN_STEP 1
>> +#define IMX576_ANA_GAIN_DEFAULT 0
>> +
>> +#define IMX576_REG_VTS CCI_REG16(0x0340)
>> +#define IMX576_REG_HTS CCI_REG16(0x0342)
>> +
>> +/* FIXME: Exact VBLANK limit unknown (no datasheet). */
>> +#define IMX576_VBLANK_MAX 32420
>> +
>> +#define IMX576_LINK_FREQ_600MHZ (600 * HZ_PER_MHZ)
>> +#define IMX576_NUM_DATA_LANES 4
>> +
>> +/* IMX576 native and active pixel array size */
>> +static const struct v4l2_rect imx576_native_area = {
>> + .top = 0,
>> + .left = 0,
>> + .width = 5792,
>> + .height = 4464,
>> +};
>> +
>> +static const struct v4l2_rect imx576_active_area = {
>> + .top = 136,
>> + .left = 16,
>> + .width = 5760,
>> + .height = 4312,
>> +};
>> +
>> +static const char * const imx576_supply_names[] = {
>> + "avdd", /* Analog power */
>> + "dovdd", /* Digital I/O power */
>> + "dvdd", /* Digital core power */
>> +};
>> +
>> +static const struct cci_reg_sequence imx576_common_regs[] = {
>> + { CCI_REG8(0x0136), 0x18 },
>> + { CCI_REG8(0x0137), 0x00 },
>> + { CCI_REG8(0x3c7e), 0x05 },
>> + { CCI_REG8(0x3c7f), 0x07 },
>> + { CCI_REG8(0x380d), 0x80 },
>> + { CCI_REG8(0x3c00), 0x1a },
>> + { CCI_REG8(0x3c01), 0x1a },
>> + { CCI_REG8(0x3c02), 0x1a },
>> + { CCI_REG8(0x3c03), 0x1a },
>> + { CCI_REG8(0x3c04), 0x1a },
>> + { CCI_REG8(0x3c05), 0x01 },
>> + { CCI_REG8(0x3c08), 0xff },
>> + { CCI_REG8(0x3c09), 0xff },
>> + { CCI_REG8(0x3c0a), 0x01 },
>> + { CCI_REG8(0x3c0d), 0xff },
>> + { CCI_REG8(0x3c0e), 0xff },
>> + { CCI_REG8(0x3c0f), 0x20 },
>> + { CCI_REG8(0x3f89), 0x01 },
>> + { CCI_REG8(0x4b8e), 0x18 },
>> + { CCI_REG8(0x4b8f), 0x10 },
>> + { CCI_REG8(0x4ba8), 0x08 },
>> + { CCI_REG8(0x4baa), 0x08 },
>> + { CCI_REG8(0x4bab), 0x08 },
>> + { CCI_REG8(0x4bc9), 0x10 },
>> + { CCI_REG8(0x5511), 0x01 },
>> + { CCI_REG8(0x560b), 0x5b },
>> + { CCI_REG8(0x56a7), 0x60 },
>> + { CCI_REG8(0x5b3b), 0x60 },
>> + { CCI_REG8(0x5ba7), 0x60 },
>> + { CCI_REG8(0x6002), 0x00 },
>> + { CCI_REG8(0x6014), 0x01 },
>> + { CCI_REG8(0x6118), 0x0a },
>> + { CCI_REG8(0x6122), 0x0a },
>> + { CCI_REG8(0x6128), 0x0a },
>> + { CCI_REG8(0x6132), 0x0a },
>> + { CCI_REG8(0x6138), 0x0a },
>> + { CCI_REG8(0x6142), 0x0a },
>> + { CCI_REG8(0x6148), 0x0a },
>> + { CCI_REG8(0x6152), 0x0a },
>> + { CCI_REG8(0x617b), 0x04 },
>> + { CCI_REG8(0x617e), 0x04 },
>> + { CCI_REG8(0x6187), 0x04 },
>> + { CCI_REG8(0x618a), 0x04 },
>> + { CCI_REG8(0x6193), 0x04 },
>> + { CCI_REG8(0x6196), 0x04 },
>> + { CCI_REG8(0x619f), 0x04 },
>> + { CCI_REG8(0x61a2), 0x04 },
>> + { CCI_REG8(0x61ab), 0x04 },
>> + { CCI_REG8(0x61ae), 0x04 },
>> + { CCI_REG8(0x61b7), 0x04 },
>> + { CCI_REG8(0x61ba), 0x04 },
>> + { CCI_REG8(0x61c3), 0x04 },
>> + { CCI_REG8(0x61c6), 0x04 },
>> + { CCI_REG8(0x61cf), 0x04 },
>> + { CCI_REG8(0x61d2), 0x04 },
>> + { CCI_REG8(0x61db), 0x04 },
>> + { CCI_REG8(0x61de), 0x04 },
>> + { CCI_REG8(0x61e7), 0x04 },
>> + { CCI_REG8(0x61ea), 0x04 },
>> + { CCI_REG8(0x61f3), 0x04 },
>> + { CCI_REG8(0x61f6), 0x04 },
>> + { CCI_REG8(0x61ff), 0x04 },
>> + { CCI_REG8(0x6202), 0x04 },
>> + { CCI_REG8(0x620b), 0x04 },
>> + { CCI_REG8(0x620e), 0x04 },
>> + { CCI_REG8(0x6217), 0x04 },
>> + { CCI_REG8(0x621a), 0x04 },
>> + { CCI_REG8(0x6223), 0x04 },
>> + { CCI_REG8(0x6226), 0x04 },
>> + { CCI_REG8(0x6b0b), 0x02 },
>> + { CCI_REG8(0x6b0c), 0x01 },
>> + { CCI_REG8(0x6b0d), 0x05 },
>> + { CCI_REG8(0x6b0f), 0x04 },
>> + { CCI_REG8(0x6b10), 0x02 },
>> + { CCI_REG8(0x6b11), 0x06 },
>> + { CCI_REG8(0x6b12), 0x03 },
>> + { CCI_REG8(0x6b13), 0x07 },
>> + { CCI_REG8(0x6b14), 0x0d },
>> + { CCI_REG8(0x6b15), 0x09 },
>> + { CCI_REG8(0x6b16), 0x0c },
>> + { CCI_REG8(0x6b17), 0x08 },
>> + { CCI_REG8(0x6b18), 0x0e },
>> + { CCI_REG8(0x6b19), 0x0a },
>> + { CCI_REG8(0x6b1a), 0x0f },
>> + { CCI_REG8(0x6b1b), 0x0b },
>> + { CCI_REG8(0x6b1c), 0x01 },
>> + { CCI_REG8(0x6b1d), 0x05 },
>> + { CCI_REG8(0x6b1f), 0x04 },
>> + { CCI_REG8(0x6b20), 0x02 },
>> + { CCI_REG8(0x6b21), 0x06 },
>> + { CCI_REG8(0x6b22), 0x03 },
>> + { CCI_REG8(0x6b23), 0x07 },
>> + { CCI_REG8(0x6b24), 0x0d },
>> + { CCI_REG8(0x6b25), 0x09 },
>> + { CCI_REG8(0x6b26), 0x0c },
>> + { CCI_REG8(0x6b27), 0x08 },
>> + { CCI_REG8(0x6b28), 0x0e },
>> + { CCI_REG8(0x6b29), 0x0a },
>> + { CCI_REG8(0x6b2a), 0x0f },
>> + { CCI_REG8(0x6b2b), 0x0b },
>> + { CCI_REG8(0x7948), 0x01 },
>> + { CCI_REG8(0x7949), 0x06 },
>> + { CCI_REG8(0x794b), 0x04 },
>> + { CCI_REG8(0x794c), 0x04 },
>> + { CCI_REG8(0x794d), 0x3a },
>> + { CCI_REG8(0x7951), 0x00 },
>> + { CCI_REG8(0x7952), 0x01 },
>> + { CCI_REG8(0x7955), 0x00 },
>> + { CCI_REG8(0x9004), 0x10 },
>> + { CCI_REG8(0x9200), 0xa0 },
>> + { CCI_REG8(0x9201), 0xa7 },
>> + { CCI_REG8(0x9202), 0xa0 },
>> + { CCI_REG8(0x9203), 0xaa },
>> + { CCI_REG8(0x9204), 0xa0 },
>> + { CCI_REG8(0x9205), 0xad },
>> + { CCI_REG8(0x9206), 0xa0 },
>> + { CCI_REG8(0x9207), 0xb0 },
>> + { CCI_REG8(0x9208), 0xa0 },
>> + { CCI_REG8(0x9209), 0xb3 },
>> + { CCI_REG8(0x920a), 0xb7 },
>> + { CCI_REG8(0x920b), 0x34 },
>> + { CCI_REG8(0x920c), 0xb7 },
>> + { CCI_REG8(0x920d), 0x36 },
>> + { CCI_REG8(0x920e), 0xb7 },
>> + { CCI_REG8(0x920f), 0x37 },
>> + { CCI_REG8(0x9210), 0xb7 },
>> + { CCI_REG8(0x9211), 0x38 },
>> + { CCI_REG8(0x9212), 0xb7 },
>> + { CCI_REG8(0x9213), 0x39 },
>> + { CCI_REG8(0x9214), 0xb7 },
>> + { CCI_REG8(0x9215), 0x3a },
>> + { CCI_REG8(0x9216), 0xb7 },
>> + { CCI_REG8(0x9217), 0x3c },
>> + { CCI_REG8(0x9218), 0xb7 },
>> + { CCI_REG8(0x9219), 0x3d },
>> + { CCI_REG8(0x921a), 0xb7 },
>> + { CCI_REG8(0x921b), 0x3e },
>> + { CCI_REG8(0x921c), 0xb7 },
>> + { CCI_REG8(0x921d), 0x3f },
>> + { CCI_REG8(0x921e), 0x7f },
>> + { CCI_REG8(0x921f), 0x77 },
>> + { CCI_REG8(0x99af), 0x0f },
>> + { CCI_REG8(0x99b0), 0x0f },
>> + { CCI_REG8(0x99b1), 0x0f },
>> + { CCI_REG8(0x99b2), 0x0f },
>> + { CCI_REG8(0x99b3), 0x0f },
>> + { CCI_REG8(0x99e1), 0x0f },
>> + { CCI_REG8(0x99e2), 0x0f },
>> + { CCI_REG8(0x99e3), 0x0f },
>> + { CCI_REG8(0x99e4), 0x0f },
>> + { CCI_REG8(0x99e5), 0x0f },
>> + { CCI_REG8(0x99e6), 0x0f },
>> + { CCI_REG8(0x99e7), 0x0f },
>> + { CCI_REG8(0x99e8), 0x0f },
>> + { CCI_REG8(0x99e9), 0x0f },
>> + { CCI_REG8(0x99ea), 0x0f },
>> + { CCI_REG8(0xe286), 0x31 },
>> + { CCI_REG8(0xe2a6), 0x32 },
>> + { CCI_REG8(0xe2c6), 0x33 },
>> + { CCI_REG8(0x4038), 0x00 },
>> + { CCI_REG8(0x9856), 0xa0 },
>> + { CCI_REG8(0x9857), 0x78 },
>> + { CCI_REG8(0x9858), 0x64 },
>> + { CCI_REG8(0x986e), 0x64 },
>> + { CCI_REG8(0x9870), 0x3c },
>> + { CCI_REG8(0x993a), 0x0e },
>> + { CCI_REG8(0x993b), 0x0e },
>> + { CCI_REG8(0x9953), 0x08 },
>> + { CCI_REG8(0x9954), 0x08 },
>> + { CCI_REG8(0x996b), 0x0f },
>> + { CCI_REG8(0x996d), 0x0f },
>> + { CCI_REG8(0x996f), 0x0f },
>> + { CCI_REG8(0x998e), 0x0f },
>> + { CCI_REG8(0xa101), 0x01 },
>> + { CCI_REG8(0xa103), 0x01 },
>> + { CCI_REG8(0xa105), 0x01 },
>> + { CCI_REG8(0xa107), 0x01 },
>> + { CCI_REG8(0xa109), 0x01 },
>> + { CCI_REG8(0xa10b), 0x01 },
>> + { CCI_REG8(0xa10d), 0x01 },
>> + { CCI_REG8(0xa10f), 0x01 },
>> + { CCI_REG8(0xa111), 0x01 },
>> + { CCI_REG8(0xa113), 0x01 },
>> + { CCI_REG8(0xa115), 0x01 },
>> + { CCI_REG8(0xa117), 0x01 },
>> + { CCI_REG8(0xa119), 0x01 },
>> + { CCI_REG8(0xa11b), 0x01 },
>> + { CCI_REG8(0xa11d), 0x01 },
>> + { CCI_REG8(0xaa58), 0x00 },
>> + { CCI_REG8(0xaa59), 0x01 },
>> + { CCI_REG8(0xab03), 0x10 },
>> + { CCI_REG8(0xab04), 0x10 },
>> + { CCI_REG8(0xab05), 0x10 },
>> + { CCI_REG8(0xad6a), 0x03 },
>> + { CCI_REG8(0xad6b), 0xff },
>> + { CCI_REG8(0xad77), 0x00 },
>> + { CCI_REG8(0xad82), 0x03 },
>> + { CCI_REG8(0xad83), 0xff },
>> + { CCI_REG8(0xae06), 0x04 },
>> + { CCI_REG8(0xae07), 0x16 },
>> + { CCI_REG8(0xae08), 0xff },
>> + { CCI_REG8(0xae09), 0x04 },
>> + { CCI_REG8(0xae0a), 0x16 },
>> + { CCI_REG8(0xae0b), 0xff },
>> + { CCI_REG8(0xaf01), 0x04 },
>> + { CCI_REG8(0xaf03), 0x0a },
>> + { CCI_REG8(0xaf05), 0x18 },
>> + { CCI_REG8(0xb048), 0x0a },
>> +};
>> +
>> +static const struct cci_reg_sequence mode_2880x2156_regs[] = {
>> + { CCI_REG8(0x0112), 0x0a },
>> + { CCI_REG8(0x0113), 0x0a },
>> + { CCI_REG8(0x0114), 0x03 },
>> + { CCI_REG8(0x0342), 0x0c },
>> + { CCI_REG8(0x0343), 0x5d },
>> + { CCI_REG8(0x0344), 0x00 },
>> + { CCI_REG8(0x0345), 0x00 },
>> + { CCI_REG8(0x0346), 0x00 },
>> + { CCI_REG8(0x0347), 0x00 },
>> + { CCI_REG8(0x0348), 0x16 },
>> + { CCI_REG8(0x0349), 0x7f },
>> + { CCI_REG8(0x034a), 0x10 },
>> + { CCI_REG8(0x034b), 0xd7 },
>> + { CCI_REG8(0x0220), 0x62 },
>> + { CCI_REG8(0x0900), 0x01 },
>> + { CCI_REG8(0x0901), 0x22 },
>> + { CCI_REG8(0x0902), 0x08 },
>> + { CCI_REG8(0x3140), 0x00 },
>> + { CCI_REG8(0x3246), 0x81 },
>> + { CCI_REG8(0x3247), 0x81 },
>> + { CCI_REG8(0x0401), 0x00 },
>> + { CCI_REG8(0x0404), 0x00 },
>> + { CCI_REG8(0x0405), 0x10 },
>> + { CCI_REG8(0x0408), 0x00 },
>> + { CCI_REG8(0x0409), 0x00 },
>> + { CCI_REG8(0x040a), 0x00 },
>> + { CCI_REG8(0x040b), 0x00 },
>> + { CCI_REG8(0x040c), 0x0b },
>> + { CCI_REG8(0x040d), 0x40 },
>> + { CCI_REG8(0x040e), 0x08 },
>> + { CCI_REG8(0x040f), 0x6c },
>> + { CCI_REG8(0x034c), 0x0b },
>> + { CCI_REG8(0x034d), 0x40 },
>> + { CCI_REG8(0x034e), 0x08 },
>> + { CCI_REG8(0x034f), 0x6c },
>> + { CCI_REG8(0x0301), 0x05 },
>> + { CCI_REG8(0x0303), 0x04 },
>> + { CCI_REG8(0x0305), 0x04 },
>> + { CCI_REG8(0x0306), 0x00 },
>> + { CCI_REG8(0x0307), 0xaf },
>> + { CCI_REG8(0x030b), 0x02 },
>> + { CCI_REG8(0x030d), 0x04 },
>> + { CCI_REG8(0x030e), 0x00 },
>> + { CCI_REG8(0x030f), 0xd1 },
>> + { CCI_REG8(0x0310), 0x01 },
>> + { CCI_REG8(0x0b06), 0x01 },
>> + { CCI_REG8(0x3620), 0x00 },
>> + { CCI_REG8(0x3f0c), 0x00 },
>> + { CCI_REG8(0x3f14), 0x01 },
>> + { CCI_REG8(0x3f80), 0x03 },
>> + { CCI_REG8(0x3f81), 0xe8 },
>> + { CCI_REG8(0x3ffc), 0x00 },
>> + { CCI_REG8(0x3ffd), 0x26 },
>> + { CCI_REG8(0x0202), 0x07 },
>> + { CCI_REG8(0x0203), 0xd0 },
>> + { CCI_REG8(0x0224), 0x01 },
>> + { CCI_REG8(0x0225), 0xf4 },
>> + { CCI_REG8(0x3fe0), 0x03 },
>> + { CCI_REG8(0x3fe1), 0xe8 },
>> + { CCI_REG8(0x0204), 0x00 },
>> + { CCI_REG8(0x0205), 0x00 },
>> + { CCI_REG8(0x0216), 0x00 },
>> + { CCI_REG8(0x0217), 0x00 },
>> + { CCI_REG8(0x0218), 0x01 },
>> + { CCI_REG8(0x0219), 0x00 },
>> + { CCI_REG8(0x020e), 0x01 },
>> + { CCI_REG8(0x020f), 0x00 },
>> + { CCI_REG8(0x3fe2), 0x00 },
>> + { CCI_REG8(0x3fe3), 0x00 },
>> + { CCI_REG8(0x3fe4), 0x01 },
>> + { CCI_REG8(0x3fe5), 0x00 },
>> +};
>> +
>> +struct imx576 {
>> + struct device *dev;
>> + struct regmap *regmap;
>> + struct v4l2_subdev sd;
>> + struct media_pad pad;
>> + struct gpio_desc *reset_gpio;
>> + struct clk *inclk;
>> + struct regulator_bulk_data supplies[ARRAY_SIZE(imx576_supply_names)];
>> +
>> + /* V4L2 Controls */
>> + struct v4l2_ctrl_handler handler;
>> + struct v4l2_ctrl *link_freq;
>> + struct v4l2_ctrl *hblank;
>> + struct v4l2_ctrl *vblank;
>> + struct v4l2_ctrl *exposure;
>> + struct v4l2_ctrl *gain;
>> +
>> + u32 link_freq_index;
>> +};
>> +
>> +struct imx576_reg_list {
>> + u32 num_of_regs;
>> + const struct cci_reg_sequence *regs;
>> +};
>> +
>> +struct imx576_mode {
>> + u32 width;
>> + u32 height;
>> + u32 hts;
>> + u32 vts;
>> + struct imx576_reg_list reg_list;
>> +};
>> +
>> +static const struct imx576_mode supported_modes_10bit[] = {
>> + {
>> + .width = 2880,
>> + .height = 2156,
>> + .hts = 3165,
>> + .vts = 2172,
>> + .reg_list = {
>> + .num_of_regs = ARRAY_SIZE(mode_2880x2156_regs),
>> + .regs = mode_2880x2156_regs,
>> + },
>> + },
>> +};
>
>No mode tables please. Control the analog crop and binning through the
>selection and format APIs.
>
>> +
>> +static const s64 link_freq[] = {
>> + IMX576_LINK_FREQ_600MHZ,
>
>The link frequency should be selectable from DT, with PLL parameters (if
>any) computed by the driver.

I don't have the full datasheet, so this cannot be implemented properly.

Best Regards,
Himanshu