[PATCH v2 05/10] arm64: dts: qcom: shikra: Add cpufreq-hw, EPSS L3 interconnect and OPP tables
From: Komal Bajaj
Date: Sat May 30 2026 - 14:32:47 EST
Add cpufreq-hw node to support cpufreq scaling on Qualcomm Shikra SoCs.
Also, add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP
tables required to scale DDR and L3 per freq-domain on Shikra SoC.
Co-developed-by: Aastha Pandey <aastha.pandey@xxxxxxxxxxxxxxxx>
Signed-off-by: Aastha Pandey <aastha.pandey@xxxxxxxxxxxxxxxx>
Co-developed-by: Imran Shaik <imran.shaik@xxxxxxxxxxxxxxxx>
Signed-off-by: Imran Shaik <imran.shaik@xxxxxxxxxxxxxxxx>
Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@xxxxxxxxxxxxxxxx>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@xxxxxxxxxxxxxxxx>
Co-developed-by: Sayantan Chakraborty <sayantan.chakraborty@xxxxxxxxxxxxxxxx>
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@xxxxxxxxxxxxxxxx>
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
Signed-off-by: Komal Bajaj <komal.bajaj@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 125 +++++++++++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 3cdabe718714..6c0cfd73cb70 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interconnect/qcom,shikra.h>
@@ -44,6 +45,14 @@ cpu0: cpu@0 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu1: cpu@100 {
@@ -54,6 +63,14 @@ cpu1: cpu@100 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu2: cpu@200 {
@@ -64,6 +81,14 @@ cpu2: cpu@200 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu3: cpu@300 {
@@ -74,6 +99,14 @@ cpu3: cpu@300 {
next-level-cache = <&l2_3>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <489>;
+ clocks = <&cpufreq_hw 1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
l2_3: l2-cache {
compatible = "cache";
@@ -132,6 +165,71 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-peak-kBps = <1200000 17817600>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <2188000 25804800>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ opp-peak-kBps = <3072000 30105600>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <4068000 38707200>;
+ };
+
+ opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <6220000 43008000>;
+ };
+
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+ };
+
+ cpu3_opp_table: opp-table-cpu3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <2188000 25804800>;
+ };
+
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-peak-kBps = <3072000 30105600>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <4068000 38707200>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <6220000 43008000>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
@@ -1820,6 +1918,33 @@ frame@f42d000 {
status = "disabled";
};
};
+
+ epss_l3: interconnect@fd90000 {
+ compatible = "qcom,shikra-epss-l3";
+ reg = <0x0 0x0fd90000 0x0 0x1000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
+ cpufreq_hw: cpufreq@fd91000 {
+ compatible = "qcom,shikra-epss";
+ reg = <0x0 0x0fd91000 0x0 0x1000>,
+ <0x0 0x0fd92000 0x0 0x1000>;
+ reg-names = "freq-domain0",
+ "freq-domain1";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "dcvsh-irq-0",
+ "dcvsh-irq-1";
+
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
};
timer {
--
2.34.1