[PATCH v3 2/5] arm64: dts: imx93-var-som-symphony: enable UART7
From: Stefano Radaelli
Date: Wed Jun 03 2026 - 04:35:35 EST
From: Stefano Radaelli <stefano.r@xxxxxxxxxxxxx>
Enable UART7 on the Symphony carrier board and add its pinctrl
configuration.
Signed-off-by: Stefano Radaelli <stefano.r@xxxxxxxxxxxxx>
---
v2->v3:
-
v1->v2:
-
.../boot/dts/freescale/imx93-var-som-symphony.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts
index c736127c7115..77377127c18c 100644
--- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts
@@ -35,6 +35,7 @@ aliases {
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
+ serial6 = &lpuart7;
};
@@ -305,6 +306,12 @@ &lpuart6 {
status = "okay";
};
+&lpuart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart7>;
+ status = "okay";
+};
+
&usbotg1 {
dr_mode = "otg";
hnp-disable;
@@ -441,6 +448,13 @@ MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e
>;
};
+ pinctrl_uart7: uart7grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e
+ MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e
--
2.47.3