RE: [PATCH 2/3] arm64: dts: renesas: rzt2h-n2h-evk: Configure ETH pins

From: Prabhakar Mahadev Lad

Date: Thu Jun 04 2026 - 10:04:19 EST


Hi Geert,

Thank you for the review.

> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 04 June 2026 14:35
> To: Prabhakar <prabhakar.csengg@xxxxxxxxx>
> Cc: magnus.damm <magnus.damm@xxxxxxxxx>; Rob Herring <robh@xxxxxxxxxx>;
> Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>; Conor Dooley
> <conor+dt@xxxxxxxxxx>; linux-renesas-soc@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Biju Das
> <biju.das.jz@xxxxxxxxxxxxxx>; Fabrizio Castro
> <fabrizio.castro.jz@xxxxxxxxxxx>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Subject: Re: [PATCH 2/3] arm64: dts: renesas: rzt2h-n2h-evk: Configure ETH
> pins
>
> Hi Prabhakar,
>
> On Thu, 28 May 2026 at 15:48, Prabhakar <prabhakar.csengg@xxxxxxxxx>
> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Update the gmac1 (ETH3) and gmac2 (ETH2) pin configurations on the
> > RZ/T2H and RZ/N2H EVK boards to comply with the electrical
> > specifications defined in Table 58.11 of the hardware user manual.
> >
> > While restructuring the nodes into pin groups, fix a copy-paste
> > comment typo in the RZ/N2H device tree where the ETH3_TXD1 pin mux
> > configuration was mistakenly labeled as ETH3_TXD0.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> i.e. will queue
> in renesas-devel for v7.3.
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> > @@ -258,23 +258,54 @@ can0_pins: can0-pins {
> > *
> > * SW2[8] ON - use pins P33_2-P33_7 and P34_0-P34_5 for Ethernet
> port 3
> > */
> > - gmac1_pins: gmac1-pins {
> > - pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK
> */
> > - <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD0
> */
> > - <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD1
> */
> > - <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD2
> */
> > - <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD3
> */
> > - <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN
> */
> > - <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK
> */
> > - <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD0
> */
> > - <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD1
> */
> > - <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD2
> */
> > - <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD3
> */
> > - <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV
> */
> > - <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* GMAC1_MDC
> */
> > - <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* GMAC1_MDIO
> */
> > - <RZT2H_PORT_PINMUX(34, 6, 0x2)>, /* ETH3_REFCLK
> */
> > - <RZT2H_PORT_PINMUX(27, 2, 0x0)>; /* IRQ3 */
> > + gmac1_pins: gmac1-group {
> > + txclk-pins {
> > + pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>; /*
> ETH3_TXCLK */
> > + drive-strength-microamp = <11800>;
> > + slew-rate = <1>;
> > + input-schmitt-disable;
> > + };
> > +
> > + txd-en-pins {
> > + pinmux = <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /*
> ETH3_TXD0 */
> > + <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /*
> ETH3_TXD1 */
> > + <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /*
> ETH3_TXD2 */
> > + <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /*
> ETH3_TXD3 */
> > + <RZT2H_PORT_PINMUX(33, 7, 0xf)>; /*
> ETH3_TXEN */
> > + drive-strength-microamp = <11800>;
> > + slew-rate = <1>;
> > + };
> > +
> > + rx-pins {
>
> I guess you want me to sort all subnodes while applying? ;-)
>
Yes please. My bad, I sorted them based on pin numbers instead of node names (I'll make a note of it for future).

Cheers,
Prabhakar