Re: [PATCH v3] drm/bridge: imx93-mipi-dsi: Fix mode validation

[Liu Ying]

On Fri, May 15, 2026 at 02:54:16PM +0800, Liu Ying wrote:
> i.MX93 MIPI DPHY PLL has limitation for matching with some pixel clock
> rates, e.g., the best DPHY PLL frequency is 445.333333MHz for a typical
> 1920x1080p@60Hz CEA/DMT display mode with a pixel clock rate running
> at 148.5MHz with 4 data lanes + RGB888 pixel in MIPI DSI sync pulse mode,
> while the expected PLL frequency is (148.5 * 24) / 4 / 2 MHz = 445.5MHz.
> Fortunately, VESA Display Monitor Timing Standard allows +/-0.5% pixel
> clock rate deviation for timings.  So, for those display modes read
> from EDID through a bridge with DRM_BRIDGE_OP_DETECT and DRM_BRIDGE_OP_EDID
> operation bit masks set, pixel clock rate could be adjusted to match
> with the PLL frequency(for the above example, the pixel clock rate is
> adjusted to be 148.444444MHz with about -0.03% deviation from the 148.5MHz
> nominal rate so that the adjusted rate matches with the 445.333333MHz PLL
> frequency).
> 
> Instead of checking the last bridge's operation bit masks against
> DRM_BRIDGE_OP_DETECT and DRM_BRIDGE_OP_EDID to determine if allowing
> +/-0.5% pixel clock rate deviation, check any bridge after this bridge,
> because the last bridge is usually a display connector bridge without
> any operation bit mask when the clock rate deviation is allowed.
> 
> Fixes: ce62f8ea7e3f ("drm/bridge: imx: Add i.MX93 MIPI DSI support")
> Fixes: 5849eff7f067 ("drm/bridge: imx93-mipi-dsi: use drm_bridge_chain_get_last_bridge()")
> Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> Signed-off-by: Liu Ying <victor.liu@xxxxxxx>
> ---
> Changes in v3:
> - Iterate over next bridges manually instead of calling
>   drm_for_each_bridge_in_chain_from() to avoid deadlock issue.  (sashiko bot)
> - Fix a typo in commit message - s/modes/mode/.
> - Link to v2: https://patch.msgid.link/20260512-imx93-mipi-dsi-fix-mode-validation-v2-1-7aec3be5da2c@xxxxxxx
> 
> Changes in v2:
> - Collect Frank's R-b tag.
> - Add an explanation to commit message about the reason why mode validation
>   checks bridge's operation bit masks.  (Dmitry)
> - Copy Dmitry.
> - Link to v1: https://lore.kernel.org/r/20260227-imx93-mipi-dsi-fix-mode-validation-v1-1-a9cd67991280@xxxxxxx
> 
> To: Liu Ying <victor.liu@xxxxxxx>
> To: Andrzej Hajda <andrzej.hajda@xxxxxxxxx>
> To: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> To: Robert Foss <rfoss@xxxxxxxxxx>
> To: Laurent Pinchart <Laurent.pinchart@xxxxxxxxxxxxxxxx>
> To: Jonas Karlman <jonas@xxxxxxxxx>
> To: Jernej Skrabec <jernej.skrabec@xxxxxxxxx>
> To: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> To: Maxime Ripard <mripard@xxxxxxxxxx>
> To: Thomas Zimmermann <tzimmermann@xxxxxxx>
> To: David Airlie <airlied@xxxxxxxxx>
> To: Simona Vetter <simona@xxxxxxxx>
> To: Frank Li <Frank.Li@xxxxxxx>
> To: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> To: Pengutronix Kernel Team <kernel@xxxxxxxxxxxxxx>
> To: Fabio Estevam <festevam@xxxxxxxxx>
> To: Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx>
> Cc: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
> Cc: imx@xxxxxxxxxxxxxxx
> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx
> ---
>  drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c | 44 ++++++++++++++++++++---------
>  1 file changed, 31 insertions(+), 13 deletions(-)

If possible, can I get a R-b or A-b tag from a drm/drm-misc maintainer/committer
so that this can be picked up with good review?

-- 
Regards,
Liu Ying