Re: [PATCH v2 1/6] dt-bindings: iommu: arm,smmu: Document interconnects property

[Bibek Kumar Patro]

On 6/8/2026 7:18 PM, Dmitry Baryshkov wrote:
> On Tue, May 26, 2026 at 08:12:02PM +0530, Bibek Kumar Patro wrote:
> > Some SoC implementations require a bandwidth vote on an interconnect
> > path before the SMMU register space is accessible. Add the optional
> > 'interconnects' property to the binding to allow platform DT nodes
> > to describe this path.
> >
> > Signed-off-by: Bibek Kumar Patro <bibek.patro@xxxxxxxxxxxxxxxx>
> > ---
> >   .../devicetree/bindings/iommu/arm,smmu.yaml        | 27 ++++++++++++++++++++++
> >   1 file changed, 27 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> > index 06fb5c8e7547cb7a92823adc2772b94f747376a6..3a677ff1a18fcdf5c0ca9ec8a017d41f9eb5ff09 100644
> > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> > @@ -243,6 +243,13 @@ properties:
> >       minItems: 1
> >       maxItems: 3
> >   
> > +  interconnects:
> > +    maxItems: 1
> > +    description:
> > +      Interconnect path to the SMMU register space. Required on SoCs
> > +      where the SMMU registers are only accessible after a bandwidth
> > +      vote has been placed on the interconnect fabric.
> > +
> >     nvidia,memory-controller:
> >       description: |
> >         A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
> > @@ -602,6 +609,26 @@ allOf:
> >           clock-names: false
> >           clocks: false
> >   
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          items:
> > +            - enum:
> > +                - qcom,qcs615-smmu-500
> > +                - qcom,qcs8300-smmu-500
> > +                - qcom,sa8775p-smmu-500
> > +                - qcom,sc7280-smmu-500
>
> Only these platforms have the interconnect which needs to be voted
> upon?

Apart from these QLI platforms, sm8650 and kaanapali would also need the 
interconnect support as per the SoC documentation, but it hasn't been 
tested yet [1].
So haven't added it as part of the ongoing series, hence as mentioned 
[2] this list might grow to accomodate other platforms.

<The list of non-QLI targets to be evaluated might be extensive>

[1]: 
https://lore.kernel.org/all/a1db573b-bcb4-44a5-89b6-6d1c76f4a18a@xxxxxxxxxxxxxxxx/
[2]: 
https://lore.kernel.org/all/0ded611e-1932-470c-8e80-9a5e94268583@xxxxxxxxxxxxxxxx/

> > +            - const: qcom,adreno-smmu
> > +            - const: qcom,smmu-500
> > +            - const: arm,mmu-500
> > +    then:
> > +      properties:
> > +        interconnects:
> > +          maxItems: 1
> > +    else:
> > +      properties:
> > +        interconnects: false
> > +
> >     - if:
> >         properties:
> >           compatible:
> >
> > --
> > 2.34.1